NXP Semiconductors QorIQ LS1028A Reference Manual page 23

1V8
VDDA/VDD/VDD_CORE
XIN
25 MHz
~
XOUT
PLL
OE(3,5)_B
From CPLD
CLKGEN_OE67_B
OE(6,7)_B
OE_Buffer
X
OE
OTP and
Control
Logic
I2C1_CH1
0x6A
No Spread S upport
in Design
*Device doesn't support switching power
rails off, even if outputs are unused.
Differential
Single-ended
The 5P49V5907B520NDGI is a programmable clock generator that generates most of the
clocks. Clock configurations are stored in its one-time programmable (OTP) memory.
The configuration in volatile memory can be changed through the I2C1_CH1 interface.
The device is accessible at 0x6A I2C 7-bit address. The frequencies are generated from a
25 MHz crystal (603-25-261 from FOX Electronics). The following table summarizes the
specifications of each clock.
Part Clock generator
identifier
U9 IDT 5P49V5907B520NDGI VDD0: FPGA_CLK_25MHz
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
NXP Semiconductors
3V3
3V3
1V8
VDDO_2
VDDO_0
VDDO
VDDO_4
VDDO_1
FOD1
OUT1
FOD2
OUT2
OUT3,5
FOD3
OUT(6,7)
FOD4
OUT4
25 MHz
OUT0_S E L_I2CB
1.8V LVCMOS
10K
5P49V5907B520NDGI
Figure 2-5. LS1028ARDB clock architecture
Table 2-3. LS1028ARDB clocks
OUT3,5:
SD1_REF_CLK1_[P, N]
SD1_REF_CLK2_[P,N]
Table continues on the next page...
Confidential Proprietary
Chapter 2 LS1028ARDB Functional Description
125 MHz LVDS
125MHz
XO
125.00 MHz
1.8V LVCMOS
1588 Header
27 MHz LVDS
100 MHz LP-HCSL
100 MHz HCSL
HOT_CLK
to CPLD
100 MHz
LP-HCSL
SLOT [1:2]_CLK_REQ
To CPLD
OE_B
Clock Specifications
• Frequency: 25 MHz
• Output type:
LVCMOS
• Operating voltage:
3.3 V
• Frequency: 100
MHz
F104
(QSGMII PHY)
LS1028
TSEC_1588_CLK_IN
TSEC_1588_CLK_IN
(EC1_RX_CLK)
DP_REFCLK_P/N
2
SD1_REF_CLK[1:2]
DIFF_SYSCLK_(P/N)
PEx Conn.
3
SLOTn_REFCLK_[P,N]
3
SLOT [1:2]_PRES ENT_B
Destination
CPLD
SerDes1
controller
23