NXP Semiconductors QorIQ LS1028A Reference Manual page 61

Chapter 4
Qixis Programming Model
This chapter describes the contents of the register block (the BCSR - Board Control /
Status Registers). These are contained within the system controller FPGA or CPLD, and
may be used to control and monitor the target system. These registers are accessible over
one or more system-specific interfaces, typically I2C, JTAG or an embedded processor.
Refer to the system reference manual for these connection details. In all cases, each
interface will use the 12-bit base address supplied in the definitions below.
This table shows the register memory map for Qixis.
Offset
000h Identification (ID)
001h Board Version (VER)
002h Qixis Version (QVER)
003h Programming Model (MODEL)
004h Minor Revision (MINOR)
005h General Control (CTL)
006h Auxiliary (AUX)
009h System Status (STAT_SYS)
00Ah Alarm (ALARM)
00Bh Presence Detect 1 (STAT_PRES1)
00Ch Presence Detect 2 (STAT_PRES2)
00Dh Misc Status (STAT_MISC)
00Eh LED Control (LED)
010h Reconfiguration Control (RCFG)
01Dh USB Control (USB_STAT)
01Eh USB Control (USB_CTL)
01Fh Watchdog (WATCH)
021h Power Control 2 (PWR_CTL2)
024h Power Status 0 (PWR_MSTAT)
025h Power Status 1 (PWR_STAT1)
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
NXP Semiconductors
Table 4-1. Qixis Register Memory Map
Register
Table continues on the next page...
Confidential Proprietary
Width Access Reset value
(In bits)
8 RO 01000111b
8 RO 00010001b
8 RO 00000001b
8 RO 01000000b
8 RW 00000001b
8 RW 00001000b
8 RW 00000000b
8 RO 00000000b
8 RO 00000000b
8 RO 0110xxxxb
8 RO xxxx1111b
8 RW 10000000b
8 RW 00000000b
8 RW 0001x00xb
8 RW 00000001b
8 RW 00xx0000b
8 RW xxxxxxxb
8 RW 00000000b
8 RO 110010xxb
8 RO 1xxx1111b
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