NXP Semiconductors QorIQ LS1028A Reference Manual page 21

12V
12V
12V
VIN
3.3V
LTC7151S 3V3
5V
LT8609S 3V3
2.5V
VR500 SW2
1.8V
VR500 SW3
1.35V
VR500 SW4
1.0V, LDO2
VR500 SW1, LDO2
VDD (0.9/1V)
LTC7151S VDD
LDO4
VR500 LDO4
DDR4 (1.2V, VTT, VREF)
MC34716
RST_OUT (to CPLD)
VR500 RST_OUT
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
NXP Semiconductors
12V
3.3V
VIN VIN
LTC7151S LT8609SEV
(12V => 3.3V) (12V => 5V)
PS_3V3_PG
EN EN
PG
3.3V
VIN
VR500 V9
SW1
SW2
SW4
SW3
PS_3V3_PG
EN RST_OUT
LDO2
LDO4
From DC jack
1.8ms
soft-start from 12V
3.87ms
soft-start from 3.3V PG
PG
6ms +
Figure 2-4. Power up voltage sequence
Confidential Proprietary
Chapter 2 LS1028ARDB Functional Description
5V
PS_V5V0_PG
1V
2.5V
1.35V
1.8V
RST_POR_B
PS_VDD_EN
PS_DDR_EN
12V
VDD
VIN
LTC7151S
(12V => 1V/
0.9V)
PS_VDD_PG
EN
PG
3.3V
VDD
VIN
MC34716EP/R2
(12V => 1.2V
=> VTT, VREF)
PS_DDR_PG_B
EN PG_B
2.5ms + 1ms
VR500 SEQ2 internally programmed
VR500 SEQ3 internally programmed
1ms
VR500 SEQ4 internally programmed
1ms
VR500 SEQ5 internally programmed
1ms
2ms
soft-start after LDO2 (PS_VDD_EN)
tss
3ms
VR500 SEQ8 internally programmed
3.2ms
soft-start after LDO4 (PS_DDR_EN)
2ms
Internal delay from last SEQ EVENT
To CPLD
To CPLD
To CPLD
To CPLD
21