Connectors - NXP Semiconductors QorIQ LS1028A Reference Manual

Table 2-6. Hardware bootstrap settings for QSGMII PHY (continued)
Setting
MODE
2.8.3 IEEE 1588 interface
The LS1028A processor provides support for the IEEE 1588
(PTP), which works in tandem with ENETC to time-stamp the incoming packets. A 12-
pin header (J11) is provided on the board to allow support for 1588 protocol. The SMA
connector (J12) is used to analyze time synchronization by measuring the pulse per
second (PPS) signal.
The table below lists the testing options provided by the IEEE 1588 test header.
IEEE 1588 feature
Clocks Input clock
Signals Other related signals
2.9 M.2 connectors
The LS1028ARDB supports M.2 connectors (Key E and Key B) that are supported
through SerDes lanes 2 and 3.
One M.2 Key E connector (J16) is connected through the LYNX36 SerDes lane 2. This
connector supports only 1630 and 2230 PCIe Gen3 card types to provide wireless
connectivity including Wi-Fi, Bluetooth, and NFC.
The other M.2 Key E connector (J18) is connected through the LYNX36 SerDes lane 3.
However, lane 3 can also connect to the M.2 Key B connector (J20) as per the register
settings mentioned in
The M.2 Key B connector supports 2230 and 2242 module card types.
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
NXP Semiconductors
Figure 2-9 shows the architecture of the IEEE 1588 system.
Table 2-7. IEEE 1588 port
Specifications
ETH reference clock (to processor) is driven from an onboard 125 MHz
oscillator source. Under software configuration, it may be clocked from the
IEEE 1588 header instead.
All remaining IEEE 1588 signals are connected to the dedicated header
pins
Table 2-8 to support solid state storage devices (SSD) ( SATA 3.0).
Confidential Proprietary
Chapter 2 LS1028ARDB Functional Description
Description
• REFCLK_SEL[1:0] = 00: 125 MHz is used as REFCLK.
• COMA_MODE = 0: PHY comes out of reset as soon as
reset is de-asserted.
™
precision time protocol
Description
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