NXP Semiconductors QorIQ LS1028A Reference Manual page 50

System controller
2.20.1 System configuration
The system controller uses switches to configure the target system into various modes.
Switches are sampled and stored in BRDCFG and DUTCFG registers. BRDCFG
registers are always active, and software may change them to result in immediate changes
to the system configuration. DUTCFG registers are used to control processor
configuration pins that are only sampled during PORESET_B, such as RCW_SRC in
DUTCFG0. Changes to DUTCFG registers only take effect on the next reset or
reconfiguration event. The following figure shows the configuration hardware
arrangement.
Note that switches cause a short to ground when closed. To make it easier to set and read
switches, values are inverted in the CPLD, so that when a switch is on, the value used is
1.
All switches can be read from software to easily determine the system configuration for
reporting purposes (see the "Core Management Space Registers" section of the "CPLD
Programming Model" chapter).
The table below describes the LS1028A configuration signals.
Configuration signal LS1028A primary
CFG_RCW_SRC0 UART2_SOUT
CFG_RCW_SRC1 UART1_SOUT
CFG_RCW_SRC2 ASLEEP
CFG_RCW_SRC3 CLK_OUT
1
TEST_SEL_B TEST_SEL
CFG_SVR[0:1] XSPI_CS0_B
XSPI0_CS1_B
CFG_ENG_USE0 XSPI_SCK
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
50
Figure 2-20. Configuration sampling
Table 2-19. Processor configuration settings
DIP switch
signal
SW1[1:4]
SW3[1]
-
-
Confidential Proprietary
CPLD register
DUTCFG0[3:0] Specifies RCW fetch location
DUTCFG2[0] Silicon variations
DUTCFG2[2:1] -
DUTCFG11[7] Configures processor to use
differential SYSCLK.
Description
NXP Semiconductors