Dut Configuration Registers; Dut Configuration 0 (Dutcfg0) - NXP Semiconductors QorIQ LS1028A Reference Manual

DUT Configuration Registers

Field
-
3-2 Manages the uBUS2 IRQ input pin:
U2IRQ 00= IRQ pin treated as active-low interrupt input.
01= IRQ pin treated as active-high interrupt input.
10= IRQ pin treated as output, asserted low.
11= IRQ pin treated as output, asserted high.
1-0 Manages the uBUS2 RST output pin:
U2RST 00= RST pin tri-stated.
01= reserved.
10= RST pin treated as output, asserted low.
11= RST pin treated as output, asserted high.
4.48 DUT Configuration Registers
This block of registers control the configuration of the DUT (Device Under Test).
DUTCFG registers, unlike BRDCFG registers, are not always driven - they are driven
only during the reset configuration sampling interval (PORESET_B assertion), and
remain tri-stated thereafter. Refer to the device hardware specification for hardware pin-
sampled timing parameters.

4.49 DUT Configuration 0 (DUTCFG0)

4.49.1 Address
Register
DUTCFG0 060h
4.49.2 Function
The DUTCFG0 register is used to the RCW location setting (cfg_rcw_src).
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
106
Function
Offset
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