NXP Semiconductors QorIQ LS1028A Reference Manual page 52

System controller
Controller Step
2
3
4
5
6
7
8
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
52
Table 2-21. Reset sequence (continued)
Action
Wait for reset clear.
Sample switches.
Drive configuration values.
Release resets.
Tristate reset-sampled pins.
Processor reset.
Reset sequence complete.
Confidential Proprietary
Description
• XSPI_x8_MEM_RST_B
• RST_eMMC_B
• RST_I2CMUX_B
• uBUS1_RST
• uBUS2_RST
The LS1028A processor asserts ASLEEP and
HRESET_B in response. ASLEEP is monitored with an
LED, otherwise the signals are ignored.
Wait for reset assertion to be released. The reset
sequencer will stall as long as any of the following reset
inputs is asserted:
• CWJTAG_RST_B
• SW_RST_B
Internal registers are reset to default values.
Registers that default to switch values are set now.
Reset-sampled configuration signals are driven:
• CFG_RCW_SRC[3:0]
• CFG_SVR[0:1]
• CFG_ENG_USE[0]
Static (constant) configuration signals are driven:
• CFG_XSPI_MAP[0:3]
• CFG_MUX_I2C2
• CFG_MUX_I2C3
• CFG_MEM_WP
• CFG_MUX_UART2_SEL0
• CFG_MUX_uBUS1_UART_B
• CFG_MUX_uBUS2_UART_B
• CFG_MUX_uBUS1_SPI_B
• CFG_MUX_uBUS2_SPI_B
• CFG_MUX_uBUS1_PWM_B
• CFG_MUX_uBUS2_PWM_B
Release all resets shown in reset sequencer step 1.
The processor samples reset pins at this time.
A fixed time period after step 5:
Tristate configuration signals drive outputs.
This ensures proper configuration hold time.
The CPLD is no longer involved in reset activity.
The LS1028A processor begins loading RCW data from
the specified RCW source location.
When RCW loading is complete, the LS1028A processor
de-asserts HRESET_B and ASLEEP.
If RCW data is correct, then the system starts running
the code. If there is an error, then RESET_REQ_B is
asserted and the system halts.
The CPLD has finished reset management.
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