Ddr Interface - NXP Semiconductors QorIQ LS1028A Reference Manual

DDR interface

Part Clock generator
identifier
2
Y2 125 MHz crystal oscillator
(KC5032A125.000C1GE00)
Y3 25 MHz crystal
1. The enable/disable for 100 MHz clocks to the M.2 connectors (J16 and J18/J20) is controlled by CPLD. The CPLD detects
the CARD presence on the M.2 slots and enables the OUT 6 and 7 of the clock generator accordingly. Since, both the
outputs are controlled from the same OE, 100 MHz clocks to the M.2 slots are enabled even if only one of the M.2 slots is
populated.
2. The Y2 oscillator provides an option for stable 125 MHz CLK_IN to the 1588 block. The option can be enabled by
mounting R388 and removing R387 that is mounted on the board by default.
2.4 DDR interface
The LS1028ARDB board connects four 1G x8 DDR4 SDRAM memory chips supporting
data transfer rates of up to 1.6 GT/s and one 1G x8 DDR4 SDRAM memory chip
supporting ECC.
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
24
Table 2-3. LS1028ARDB clocks (continued)
Clock
1
OUT6, 7 :
PEXM2_1_REFCLK_[P,N]
PEXM2_2_REFCLK_[P,N]
OUT4:
DIFF_SYSCLK[P, N]
OUT2:
DP_REFCLK_[P, N]
OUT1:
125M0_LVDS_REF_CLK_[P,N]
EC1_125MHz_CLK
(EC1_RX_CLK)
ETH_XTALIN
ETH_XTALOUT
Confidential Proprietary
Specifications
• Output type: LP-
HCSL
• Operating voltage:
1.8 V
• Frequency: 100 M.2 connectors 1
MHz and 2
• Output type: LP-
HCSL
• Operating voltage:
1.8 V
• Frequency: 100 DIFF_SYSCLK
MHz
• Output type: HCSL
• Operating voltage:
3.3 V
• Frequency: 27 MHz Display Port
• Output type: LVDS
• Operating voltage:
3.3 V
• Frequency: 125 QSGMII PHY
MHz
• Output type: LVDS
• Operating voltage:
3.3 V
• Frequency: 125 Ethernet
MHz controller / IEEE
• Output type: 1588 port
LVCMOS
• Operating voltage:
1.8 V
Frequency: 25 MHz SGMII PHY
NXP Semiconductors
Destination