NXP Semiconductors QorIQ LS1028A Reference Manual page 49

DIP Switch Controls:
 SW_RCW_SRC[3:0]
SW_RST_MODE

sw_enguse[0]

SW_TESTSEL_B

SW_SVR[0:1]

 SW_UART2MAP[1:0]
SW_UCLICK_PWMMAP

SW_UCLICK_SPIMAP

SW_CPU_FORCE[1:0]

SW_BYPASS_B

 SW_CFG_WP
 SW_BOOTBOX_B
CPLD
MAX CPLDs do not
have a pulldown
option, so switches
are implemented as
shown. The CPLD
inverts the signals,
so that UP = ON.
IRQ_RTC_B
IRQ_QSGMII_B
uBUS1_INT
uBUS2_INT
IRQ_ETH_B
I2C1_SDA
I2C1_SCL
PRESENT_SLOT[1:2]_B
PRESENT_PROC_B
ROTATION_ERR_B
THERM_WARN_B
THERM_ALERT_B
CPLD_PROG_TCK
2 1
3.3V
CPLD_PROG_TDO
3
4
CPLD_PROG_TMS
5
6
7
8
CPLD_PROG_TDI
10 9
Samtec
HTST-105-01-SM-DV
Figure 2-19. System controller architecture (continued)
The system controller is implemented in a 100-ball FBGA Altera CPLD,
EPM2210F256C5N.
The system controller is powered using the 3.3 V and 1.8 V regulators. The CPLD
controls the reset of the board peripherals including the LS10128A processor. However,
the CPLD does not control power sequencing.
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
NXP Semiconductors
SW1
SW1[1:8]
CTS
218-8LPST
SW2
SW2[1:8]
CTS
218-8LPST
SW3
SW3[1:8]
CTS
218-8LPST
CPLD
CPLD
3V3
Confidential Proprietary
Chapter 2 LS1028ARDB Functional Description
POR_cfg (LS1028 & LS1043INT
POR_cfg
GPIO1_25 for INT
GPIO
ASLEEP (cfg_soc_use)
ASLEEP
TEST_SEL_B
TBSCAN_EN_B
TEST_SEL_B
CFG_XSPI_MAP[3:0]
CFG_MEM_WP
CFG_MUX_UART2_SEL0
CFG_MUX_uBUS1_UART_B
CFG_MUX_uBUS2_UART_B
CFG_MUX_uBUS1_SPI_B
CFG_MUX_uBUS2_SPI_B
CFG_MUX_uBUS1_PWM_B
CFG_MUX_uBUS2_PWM_B
CFG_XTEST
LED_STAT[7:0]
LED_ASLEEP
LED_PASS
LED_FAIL
LED_PORST
LED_RSTREQ
LED_THERM
LS1028
to Flex SPI
to I2C Memory
to UART2 &
MikroClick modules
Tes tPoint
LEDs of
indicated
color s
(RED = alert)
49