NXP Semiconductors QorIQ LS1028A Reference Manual page 95

4.37 Reset Mask 1 (RST_MASK1)
4.37.1 Address
Register
RST_MASK1 04Bh
4.37.2 Function
The RST_MASKn registers are used to block reset to a particular device, independent of
the general reset sequencer. As long as a bit is set to 1, the reset signal to that device or
devices will be blocked.
RST_MASKn bits have the same bit definition as their counterparts in RST_FORCEn;
refer to Table 5-53 for details.
Note that RST_MASK bits are cleared on AUX reset, and so are usually only cleared by
software. This is very different from the RST_FORCE registers.
4.37.3 Diagram
Bits 7
R
XSPI
W
ARST 0
4.37.4 Fields
Field
7 1= Mask RST_XSPI_B.
XSPI
6-5 Reserved.
-
4 1= Mask RST_I2CMUX_B.
I2CMUX
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
NXP Semiconductors
6 5 4
I2CMUX
00 0
Table continues on the next page...
Confidential Proprietary
Chapter 4 Qixis Programming Model
Offset
3 2
EMMC
0
Function
1 0
MEM
00 0
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