NXP Semiconductors QorIQ LS1028A Reference Manual page 48

System controller
PUSH
MAX811
BUTTON
JTAG
HEADER
PEXM2_1_CLKREQ0_B
CLOCK Control for M.2
PEXM2_2_CLKREQ0_B
connectors
SATAM2_3_CLKREQ0_B
CLKGEN_OE67_B
PEXM2_1_WDISABLE1_B
Control for M.2
PEXM2_2_WDISABLE1_B
connector
SATAM2_3_DEVSLP
USB1_VBUSSW_FAULT_B
USB1 VBUS S witch
USB1_PWRFAULT
FAULT
USB2_VBUSSW_EN
USB2_ID
USB2 VBUS S witch E N
USB2_BUFF_CON_DET
and FAULTl
USB2_DRVVBUS
USB2_VBUSSW_FAULT_B
USB2_PWRFAULT
CPLD_PROG_TDI
CPLD_PROG_TDO
from JTAG
CPLD_PROG_TCK
CPLD_PROG_TMS
from CLOCK
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
48
1V8 3V3
SW_RST_B
JTAG_RST_B
CPLD
Altera
EPM2210F256C5N
FBGA100
TDI
TDO
TMS
TCK
1V8
10K
HOT_RST_B
10uF
HOT_CLK
25 MHz
1.8V LVCMOS
Figure 2-18. System controller architecture
Confidential Proprietary
Power Good
PS_5V0_PG
PS_3V3_PG From Power
POR_OUT_VR500_B
PS_1V0_PG
PS_DDR_PG_B
PS_TA_BB_VDD_PG_B
DUT_RESET_REQ_B
DUT_HRESET_B
DUT_PORESET_B
DUT_TRST_B
RST_QSGMII_B,
RST_1GETH_B
to QSGMII & SGMII PHY
PEXM2_1_PERST0_B
PEXM2_2_PERST0_B
SATAM2_3_PERST0_B
to M.2 PEX and SATA slots
RST_IEEE1588_B
to IEEE header
RST_I2C_B
to I2C devices
RST_MEM1_3V3_B
to DDR reset through a diode
XSPI_x8_MEM_RST_B
to XSPI Memory
RST_eMMC_B
to eMMC Memory
RST_I2CMUX_B
to I2C MUX Memory
uBUS1_RST
uBUS2_RST
to MIKROCLICK module
BOM_REV[2:0]
000 = "Base Rev 0"
001 = "Rev 1"
3x ...
Selectively DNP
resistors to encode
BOM rev
PCB_REV[2:0]
000 = "Rev A"
001 = "Rev B"
...
3x
Selectively DNP
resistors to
encode PCB rev
Supplies
to LS 1028A
NXP Semiconductors