Board Configuration 3 (Brdcfg3) - NXP Semiconductors QorIQ LS1028A Reference Manual

4.43.3 Diagram
7
Bits
R SD1CK1
W
RRST 00
4.43.4 Fields
Field
7-6 SerDes1 Clock #1 Rate:
SD1CK1 00= 100.000 MHz (fixed)
5-4 SerDes1 Clock #2 Rate:
SD1CK2 00= 100.000 MHz (fixed)
3-0 Reserved.
-

4.44 Board Configuration 3 (BRDCFG3)

4.44.1 Address
Register
BRDCFG3 053h
4.44.2 Function
The BRDCFG3 register controls board routing.
QorIQ LS1028A Reference Design Board Reference Manual, Rev. A, 02/2018
NXP Semiconductors
6 5 4
SD1CK2
00
Confidential Proprietary
Chapter 4 Qixis Programming Model
3 2
Function
Offset
1 0
0000
101