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NXP Semiconductors QorIQ LS1046A Manual
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NXP Semiconductors QorIQ LS1046A Manual

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NXP Semiconductors
Application Note
QorIQ LS1046A Design Checklist

1 About this document

This document provides recommendations for new designs
based on the LS1046A/LS1026A processor, which is a cost-
effective, power-efficient, and highly integrated system-on-
chip (SoC) design that extends the reach of the NXP Value
Performance line of QorIQ communications processors.
This document can also be used to debug newly-designed
systems by highlighting those aspects of a design that merit
special attention during initial system start-up.
This document applies to the LS1046A and
LS1026A devices. For a list of functionality
differences, see the appendices in QorIQ
LS1046A Reference Manual (document
LS1046ARM).

2 Before you begin

Ensure you are familiar with the following NXP collateral
before proceeding:
• QorIQ LS1046A, LS1026A Data Sheet (document
LS1046A)
• QorIQ LS1046A Reference Manual (document
LS1046ARM)
NOTE
Document Number: AN5252
Contents
1
About this document........................... ...................... 1
2
Before you begin............................... ........................1
3
Simplifying the first phase of design.........................2
4
Power design recommendations.......... ..................... 5
5
Interface recommendations......................................15
6
Thermal................................ ................................... 54
7
Revision history.......................... ............................ 56
Rev. 2, 06/2020

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Summary of Contents for NXP Semiconductors QorIQ LS1046A

  • Page 1: Table Of Contents

    QorIQ LS1046A Reference Manual (document LS1046ARM). 2 Before you begin Ensure you are familiar with the following NXP collateral before proceeding: • QorIQ LS1046A, LS1026A Data Sheet (document LS1046A) • QorIQ LS1046A Reference Manual (document LS1046ARM)

  • Page 2: Simplifying The First Phase Of Design

    6x LPUART Core Complex Accelerators and Memory Control Basic Peripherals, Interconnect, and Debug Networking Elements Figure 1. LS1046A block diagram This figure shows the major functional units within the LS1026A chip. QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 3 It is strongly recommended that this document be thoroughly researched prior to starting a design with the chip. LS1046A QorIQ LS1046A, LS1026A Data Sheet www.nxp.com LS1046AFS QorIQ LS1046A and LS1026A Communication Processors - Fact Sheet www.nxp.com LS1046ARM QorIQ LS1046A Reference Manual www.nxp.com LS1046APB QorIQ LS1046A Product Brief www.nxp.com...
  • Page 4 NXP reference design (RDB) system. 3.2 Product revisions This table lists the system version register (SVR) and ARM core main ID register (TRCIDR1) values for the various chip silicon derivatives. QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...

  • Page 5: Power Design Recommendations

    Must remain powered dynamically eSDHC_DAT[0:3], switchable eSDHC_CMD, eSDHC_CLK, FTM4_CH[6:7], LPUART3, LPUART5, LPUART6 Ethernet Interface 1/2, Ethernet 1.8/2.5 V Must remain powered management interface 1 Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 6 Analog and Digital HS supply 0.9/1.0 V Tie to GND for USBPHY USB_SV Analog and Digital SS supply 0.9/1.0 V Tie to GND for USBPHY Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 7 NOTE For supported voltage/frequency/temperature range options, see the orderable part list of QorIQ LS1046A and LS1026A Multicore Communications Processors at www.nxp.com. If all USB power supplies are connected to GND when USB is not used, the JTAG IEEE Std 1149.1-2001 Boundary Scan Register (BSR) will not shift contents between TDI and TDO.
  • Page 8 PLL's resonant frequency range from a 500 kHz to 10 MHz range. Provide independent filter circuits per PLL power supply, as illustrated in the following figure. Where Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 9 • Caution: These filters are a necessary extension of the PLL circuitry and are compliant with the device specifications. Any deviation from the recommended filters is done at the user's risk. Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 10 6. Users can choose either one as they see best fit their needs, but the primary NFM type filter has two advantages: lower DC droop and easier layout than the ferrite bead solution Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 11 BLM18KG121TN1 Bulk Decoupling 3.3 V USB_HV DD capacitors capacitors 2.2 µF 2700 PF GRM155R60J225KE95 GRM155R71H272KA01 Figure 8. Alternate USB_HV power supply filter circuit Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 12 Figure 11. Primary USB_SDV power supply filter circuit BLM18KG121TN1 Bulk Decoupling USB_SDV DD capacitors capacitors 2.2 µF 2700 PF GRM155R60J225KE95 GRM155R71H272KA01 Figure 12. Alternate USB_SDV power supply filter circuit Note the following: QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 13 Power sequencing The chip requires that its power rails be applied in a specific sequence in order to ensure proper device operation. For details, see QorIQ LS1046A, LS1026A Data Sheet" (document LS1046A). 4.3.1 Configuration signals sampled at reset The signals that serve alternate functions as configuration input signals during system reset are summarized in this table.
  • Page 14 1 = Enabled (default) Default is "1". It is recommened to keep provision for optional pull-down resistor on board. "Single Oscillator Source" clock IFC_WP0_B Default is "1". Reserved. configuration (cfg_eng_use2) QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...

  • Page 15: Interface Recommendations

    (2-10 kΩ) for SDRAM DDR4 or strong pull-up resistor (50-100 Ω) for discrete/RDIMM SDRAM DDR4, be placed on this pin to the respective power supply. Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 16 D1_MDQS[0:8]_B — May be left unconnected. D1_MDQS[0:8] — May be left unconnected. D1_MDQ[0:63] — May be left unconnected. D1_MECC[0:7] — May be left unconnected. Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 17 CKE signal must be driven low. For applications requiring LS1046A to be powered off and SDRAM memory in self refresh, the CKE signal must be driven/pulled low during power ramp up, external to the SoC by hardware on the board. Refer AN4531 QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 18 The internal pull-ups are designed such that it can be overpowered by an IFC_WP[0]_B external 4.7 kΩ resistor. However, It is recommended to keep a provision for optional pull-up and pull-down resistor on board. Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 19 UART1_SOUT The functionality of these pins is These pins can be left unconnected. determined by the UART_BASE and UART1_RTS_B UART_EXT fields in the reset Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 20 These pins should be pulled high LPUART4_SIN LPUART[1:2]_SIN and through a 2-10 kΩ resistor to DV LPUART[4]_SIN is determined by or else programmed as GPIOs and outputs. Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 21 Recommend that a weak pull-up resistor these pins can be programmed as GPIO IIC4_SDA (1 kΩ)be placed on the pin to the and output. respective power supply.These pins are IIC4_SCL open-drain. QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 22 I/O type Used Not used Complete SDHC_CMD This pin should be pulled high through Program as GPIO and output. a 10-100 kΩ resistor to EV Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 23 The functionality is determined by the SPI_BASE field and SPI_EXT field in the reset configuration word (RCW[SPI_BASE] and RCW[SPI_EXT]). NOTE: External voltage select, to change voltage of external regulator. Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 24 SD Card Connections (SDR12, 25, 50, 104, and DDR50 modes) UHS-I modes, work on 1.8 V signalling. The SYNC_OUT, SYNC_IN connections are required in SDR50 and DDR50 modes only. Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 25 Card Connection in DDR mode The 8-bit operation cannot be supported due to RCW selection constraints. The DDR mode supports both 3.3 V and 1.8 V operation as per eMMC 4.4 specification. QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 26 • When non-asserted state is low, RCW[IRQ_EXT]). tied to GND or else programmed as GPIOs and ouputs. IRQ[11] This pin should be tied to nonasserted state through a 2-10 kΩ resistor. QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 27 Can be left floating as it is an determined by the ASLEEP field in output, alternately it may be the reset configuration word programmed as GPO. (RCW[ASLEEP]). 5.10 Debug and reserved pin recommendations QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 28 TD1_ANODE Connect as required. Tie to GND if not used. TD1_CATHODE Connect as required. Tie to GND if not used. D1_TPA Do not connect. These pins should be left floating. QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 29 Ensure clocks are driven from an If the PLL is unused, pull down to appropriate clock source, as per GND. SD1_REF_CLK1_P the protocol selected by the RCW SD2_REF_CLK2_N settings. Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 30 1b by the RCW. In reality, although the default 1b setting does overlap with the 0b setting in terms of Rx Equalization boost effect, the 0b setting works better for short and normal SerDes channels, while the 1b setting works better for high loss channels. QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 31 • For XFI 10.3125 Gbaud: Perform a PBI write to each lane’s LNaRECR0 register with a value of 0x0000_045F, which sets this lane’s Rx Equalization Boost bit, LNaRECR0 [RXEQ_BST] to 0b. QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 32 The functionality of the USB2_DRVVBUS signal is determined by Extended RCW PinMux Control Register (SCFG_RCWPMUXCR0) in bitfield IIC3_SCL. Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 33 USB[1/2/3]_ID: The permissible voltage range for input signal is 0 - 1.8V. 5.12.1 USB1 PHY connections This section describes the hardware connections required for the USB PHY. This figure shows the VBUS interface for the chip. QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 34 EMI1_MDC in "normal functional" mode. In "normal functional" mode, the EMI1_MDC will be actively driven and pull up resistors are not required. Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 35 Unless there is a requirement of EMI2_MDC being an open-drain, it is advised to configure EMI2_MDC in "normal functional" mode. In "normal functional" mode, the Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 36 Both, EC1 and EC2 operated using LVDD supply which supports 1.8 V/2.5 V operation. Table 24. Ethernet controller pin termination checklist Signal Name I/O type Used Not used Completed EC1 in RGMII mode Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 37 RCW[IFC_GRP_F_EXT] bits of QSPI_A_CS[0:1] reset configuration word. QSPI_B_CS[0:1] QSPI_A_DATA[0:2] If these pins are not used, they should be pulled to GND through 1 kΩ resistance. Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 38 The functionality of these signals is This pin should be pulled high through a determined by the RCW[SPI_BASE] 2-10 kΩ resistor to OV SPI_SOUT and RCW[SPI_EXT] fields. SPI_SCK This pin may be left unconnected. SPI_PCS[0:3] QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 39 RCW[IFC_GRP_E1_BASE] field in the reset configuration word. GPIO2_[13:15] The functionality of these signals is determined by the RCW[IFC_GRP_D_BASE] fields in the reset configuration word. Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 40 The functionality of these signals is determined by the RCW[USB_DRVVBUS] field in the reset configuration word. GPIO4_[30] The functionality of these signals is determined by the RCW[USB_PWRFAULT] fields in the reset configuration word. QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 41 The functionality of these signals is determined by the IIC4_SDA FTM3_FAULT bitfield in register SCFG_RCWPMUXCR0 FTM3_QD_PHA The functionality of these signals is determined by the IIC2_EXT FTM3_QD_PHB fields in the reset configuration word (RCW[IIC2_EXT]). QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 42 Not Used Completed FTM6_CH[0:1] The functionality of these signals Program as a GPIO and as an is determined by the output. FTM6_EXTCLK IFC_GRP_D_EXT fields in the reset configuration word (RCW[IFC_GRP_D_EXT]). QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 43 (RCW[EC2]). TSEC_1588_ALARM_ The functionality of these signals is OUT1 determined by the EC2 field in the reset configuration word TSEC_1588_ALARM_ (RCW[EC2]). OUT2 TSEC_1588_CLK_OUT TSEC_1588_PULSE_O Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 44 IO type Used Not Used Completed Connect to pin 4 of the ARM Cortex 10-pin header. This pin requires a 2-10 kΩ resistor to OV Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 45 The ARM® Cortex® 10-pin interface has a standard header, shown in the following figure. The connector typically has pin 7 removed as a connector key. The signal placement recommended in this figure is common to all known emulators. QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 46 18. Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions, as most have asynchronous behavior and spurious assertion gives unpredictable results. QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 47 2. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid accidentally asserting the TRST line. If BSDL testing is not being performed, ensure this switch is closed. Figure 18. JTAG interface connection QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 48 100 MHz 2-10 kΩ resistor to GND. input clock. NOTE 1. In the "Single Oscillator Source" reference clock mode supported by LS1046A, DIFF_SYSCLK/DIFF_SYSCLK_B (differential) clock inputs are used as primary QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 49 USB PLL. And, multiplexer between DIFF_SYSCLK/DIFF_SYSCLK_B inputs and DDRCLK is used to provide reference clock to the DDR PLL. The duty cycle reshaper reshapes the 125 MHz ECn_GTX_CLK125 which is fed into frame manager for transmission as ECn_GTX_CLK. QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 50 Table 41. Single oscillator source clock select Functional signals Reset configuration name Value (binary) Options IFC_WE0_B cfg_eng_use0 DIFF_SYSCLK/DIFF_SYSCLK_B (differential) Default (1) SYSCLK (single ended) Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 51 DIFF_SYSCLK LVDS 100 Ohm DIFF_SYSCLK_B Figure 20. LVDS receiver Interfacing DIFF_SYSCLK/DIFF_SYSCLK_B with other Differential Signalling levels Connection with HCSL Clock driver Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 52 100 Ω differential PWB trace 100 Ω Clock Receiver DIFF_SYSCLK_B CLK_Out Figure 22. Interfacing with LVDS clock driver (Reference only) Connection with LVPECL Clock driver Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 53 16 Ω. DIFF_SYSCLK 33 Ω Clock LVDS CLK CLK_Out 100 Ω receiver 100 Ω differential PWB trace DIFF_SYSCLK_B OVDD/2 Figure 24. Single ended connection (Reference only) QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...

  • Page 54: Thermal

    Ensure the heat sink is attached to the printed-circuit board with the spring force centered over the package. Ensure the spring force does not exceed 15 pounds force (65 Newtons). Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 55 • The die junction-to-lid-top thermal resistance • The die junction-to-board thermal resistance This figure shows the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...

  • Page 56: Revision History

    Ethernet controller pin termination recommendations • Updated description for unused pins • Added "The unused clock pin should be pulled to GND" in the note Table continues on the next page... QorIQ LS1046A Design Checklist , Rev. 2, 06/2020 NXP Semiconductors...
  • Page 57 GND through 4.7 kΩ resistor. Otherwise these pins should be configured as output GPIOs and left as unconnected" in QSPI pin termination recommendations • Updated note as "For supported voltage/frequency/temperature range options, see the orderable part list of QorIQ LS1046A and LS1026A Multicore Communications Processors at www.nxp.com." in Power pin recommendations 11/2019 •...
  • Page 58 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or Home Page: fabricate any integrated circuits based on the information in this document. NXP reserves the right to nxp.com make changes without further notice to any products herein.

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