Table of Contents
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NXP Semiconductors
Application Notes
S32G2 Vehicle Network Processor - Clock
Configuration Guide
by: NXP Semiconductors
1. Introduction
NXP's S32G2 is a family of high-performance
vehicle network processors that combines Controller
Area Network (CAN), Local Interconnect Network
(LIN), and FlexRay networking with high-data-rate
Ethernet networking. It also combines a functional
safe-core infrastructure with MPU cores and includes
high-level security features.
S32G2 supports multiple clock sources for clock
generation:
• Fast Internal RC Oscillator (FIRC) (48 MHz)
• Slow Internal RC Oscillator (SIRC) (32 KHz)
• Fast External Crystal Oscillator (FXOSC) (20
- 40 MHz)
• Phase-Locked Loops (PLLs)
• Digital Frequency Synthesizer (DFS) modules
This application note is intended to provide the user
values for commonly used PLL/DFS configurations.
This document is accompanied with an attached clock
configurator - S32G2_Clock_Configurator.xlsx. The
calculator simplifies the clock configuration process
by helping user find the recommended and validated
values of PLL parameters (MFI, MFN and DIV), DFS
parameters (MFI and MFN), MC_CGM parameters
Document Number: AN13354
Contents
1.
Introduction .................................................................... 1
2.
PLL ................................................................................ 2
3.
DFS ................................................................................ 4
4.
Clock calculator design ................................................... 6
4.1
Options tab ........................................................... 6
4.2
Configuration tab.................................................. 7
4.3
Spread spectrum tab.............................................. 8
4.4
Clock calculator key considerations....................... 9
5.
Spread Spectrum ........................................................... 10
5.1
Frequency modulation programming ................... 10
5.2
Spread Spectrum Considerations ......................... 11
5.3
Example code ..................................................... 12
6
Clock Configuration using S32DS Clocks Tool .............. 13
7
References .................................................................... 15
Rev. 1 , 11/2021
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Table of Contents
Related Manuals for NXP Semiconductors S32G2
Summary of Contents for NXP Semiconductors S32G2
-
Page 1: Table Of Contents
Configuration Guide by: NXP Semiconductors Contents 1. Introduction Introduction ..............1 NXP’s S32G2 is a family of high-performance PLL ................2 DFS ................4 vehicle network processors that combines Controller Clock calculator design ........... 6 Area Network (CAN), Local Interconnect Network Options tab ............ -
Page 2: Pll
Phase Locked Loop SSCG Spread Spectrum Clock Generation 2. PLL The document provides the coherent values for the following PLLs: 1. CORE_PLL 2. PERIPH_PLL 3. ACCEL_PLL 4. DDR_PLL S32G2 Vehicle Network Processor - Clock Configuration Guide, Rev. 1, 11/2021 NXP Semiconductors... - Page 3 RDIV are shown in the following table. Table2. RDIV values Frequency RDIV FXOSC – 20 MHz FXOSC – 24 MHz FXOSC – 40 MHz 1 or 2 FIRC – 48 MHz S32G2 Vehicle Network Processor - Clock Configuration Guide, Rev. 1, 11/2021 NXP Semiconductors...
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Page 4: Dfs
6. STEPNO : Number of steps to achieve modulation depth in frequency modulation mode. 3. DFS The document provides the coherent values for following DFS: 1. CORE_DFS 2. PERIPH_DFS S32G2 Vehicle Network Processor - Clock Configuration Guide, Rev. 1, 11/2021 NXP Semiconductors... - Page 5 1. PLL_VCO : Respective PLL_VCO frequency serves an input clock source to the DFS block. 2. MFI : Integer part of LDF. 3. MFN : Numerator of fractional LDF S32G2 Vehicle Network Processor - Clock Configuration Guide, Rev. 1, 11/2021 NXP Semiconductors...
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Page 6: Clock Calculator Design
Clock calculator design 4. Clock calculator design The S32G2 clock configurator is in the form of an interactive Microsoft Excel spreadsheet organized in multiple tabs as explained in below sub-sections. 4.1 Options tab The options tab provides an interface to select the following: 1. -
Page 7: Configuration Tab
After selecting the parameters in the options tab, the calculator provides the value for PLL parameters (MFI, MFN, DIV), DFS parameters (MFI, MFN) and MC_CGM parameters (SELCTL, DIV) in the configurations tab on the basis of the selection in the options tab. S32G2 Vehicle Network Processor - Clock Configuration Guide, Rev. 1, 11/2021 NXP Semiconductors... -
Page 8: Spread Spectrum Tab
RDIV from the drop down list. An example to calculate STEPNO and STEPSIZE for the CORE_PLL is shown below. Figure 11. Spread spectrum tab S32G2 Vehicle Network Processor - Clock Configuration Guide, Rev. 1, 11/2021 NXP Semiconductors... -
Page 9: Clock Calculator Key Considerations
Spread Spectrum Considerations. Any invalid value selection leads to the specified parameter block turning pink. User must adjust the value of specified parameter to be within range. S32G2 Vehicle Network Processor - Clock Configuration Guide, Rev. 1, 11/2021 NXP Semiconductors... -
Page 10: Spread Spectrum
This section provides the user instructions on how to enable Spread Spectrum functionality. For S32G2, Spread Spectrum clock modulation is only available for the Core, Accelerator and DDR PLLs. PLL operates in frequency modulation mode when the user sets the following bits as shown in the table below –... -
Page 11: Spread Spectrum Considerations
Equation 6 5.2.2 Modulation frequency With center-spread SSCG enabled the modulation frequencies for Core, Accelerator and DDR must be within the range as specified in the table below. S32G2 Vehicle Network Processor - Clock Configuration Guide, Rev. 1, 11/2021 NXP Semiconductors... -
Page 12: Example Code
SSCG disabled as 2000 MHz, PLL_CORE_VCO as 64 KHz, MD % as 1.5 And select the FXOSC (f ) frequency and RDIV from the drop list. S32G2 Vehicle Network Processor - Clock Configuration Guide, Rev. 1, 11/2021 NXP Semiconductors... -
Page 13: Clock Configuration Using S32Ds Clocks Tool
Visual inspection of the configured clock paths is available using the graphical clock tree. The Clocks Tool validates clock settings and provides calculations of the resulting clock frequencies. S32G2 Vehicle Network Processor - Clock Configuration Guide, Rev. 1, 11/2021 NXP Semiconductors... - Page 14 Clock Configuration using S32DS Clocks Tool Figure 17. Clocks diagram view S32G2 Vehicle Network Processor - Clock Configuration Guide, Rev. 1, 11/2021 NXP Semiconductors...
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Page 15: References
Similar clock configuration can also be done using EB tresos. 7 References 1. S32G2 Reference Manual 2. S32G2 Data Sheet NOTE S32G2-related documents are available on nxp.com S32G2 Vehicle Network Processor - Clock Configuration Guide, Rev. 1, 11/2021 NXP Semiconductors... - Page 16 Information in this document is provided solely to enable system and software How to Reach Us: implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the Home Page: nxp.com information in this document.
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