Pit Control And Status Register (Pcsrn) - Freescale Semiconductor ColdFire MCF52210 ColdFire MCF52211 ColdFire MCF52212 ColdFire MCF52213 Reference Manual

2
User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error.
20.2.1

PIT Control and Status Register (PCSRn)

The PCSRn registers configure the corresponding timer's operation.
IPSBAR 0x15_0000 (PCSR0)
Offset: 0x16_0000 (PCSR1)
15 14
R 0 0
W
Reset 0 0
Field
15–12 Reserved, must be cleared.
11–8 Prescaler. The read/write prescaler bits select the internal bus clock divisor to generate the PIT clock. To accurately
PRE predict the timing of the next count, change the PRE[3:0] bits only when the enable bit (EN) is clear. Changing
PRE[3:0] resets the prescaler counter. System reset and the loading of a new value into the counter also reset the
prescaler counter. Setting the EN bit and writing to PRE[3:0] can be done in this same write cycle. Clearing the EN
bit stops the prescaler counter.
7 Reserved, must be cleared.
6 Doze Mode Bit. The read/write DOZE bit controls the function of the PIT in doze mode. Reset clears DOZE.
DOZE 0 PIT function not affected in doze mode
1 PIT function stopped in doze mode. When doze mode is exited, timer operation continues from the state it was in
before entering doze mode.
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
13 12 11 10
0 0
PRE
0 0 0 0
Figure 20-2. PCSRn Register
Table 20-3. PCSRn Field Descriptions
PRE
0000
0001
0010
...
1101
1110
1111
9 8 7 6
0
DOZE DBG OVW
0 0 0 0
Description
Internal Bus Clock
Divisor Equivalent
0
2
1
2
2
2
...
13
2
14
2
15
2
Programmable Interrupt Timers (PIT0–PIT1)
Access: Supervisor
5 4 3
PIF
PIE
w1c
0 0 0
Decimal
1
2
4
...
8192
16384
32768
read/write
2 1 0
RLD EN
0 0 0
20-3