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M30245 Group
2.9.7 Operation of A/D Converter (in repeat sweep mode 1)
In repeat sweep 1 mode, choose functions from those listed in Table 2.9.7. Operations of the circled items are
described below. Figure 2.9.14 shows ANi pin's sweep sequence, Figure 2.9.15 shows timing chart, and Figure
2.9.16 shows the set-up procedure.
Table 2.9.7. Choosed functions
Item
O p e r a t i o n c l o c k
R e s o l u t i o n
A n a l o g i n p u t p i n
Operation
(1) Setting the A/D conversion start flag to "1" causes the A/D converter to start the conversion on voltage
input to the AN
(2) After the A/D conversion on voltage input to the AN
comparison register (conversion result) is transmitted to AD register 0.
(3) Every time the A/D converter carries out A/D conversion on a selected analog input pin, the A/D converter
carries out A/D conversion on only one unselected pin, and then the A/D converter carries out A/D conver-
sion from the AN
time conversion on a pin is completed. The A/D conversion interrupt request bit does not go to "1".
(4) The A/D converter continues operating until software goes the A/D convers
When AN
is selected
0
0
0 0
0
0
0
1
2
3
4
5
6
Figure 2.9.14. ANi pin's sweep sequence in repeat sweep mode
(1) Start AN
φ
A D
A / D
" 1 "
c o n v e r s i o n
s t a r t f l a g
" 0 "
AD register 0
A D r e g i s t e r 1
A D r e g i s t e r 2
N o t e : W h e n φ
Figure 2.9.15. Operation timing of repeat sweep 1 mode
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Set-up
D i v i d e d - b y - 4 f
A D
A D
O
b y - 3 f
/ d i v i d e d - b y - 2 f
A D
/ f
A D
O
8 - b i t / 1 0 - b i t
A n
( 1 p i n ) / A N
0
p i n s ) / A N
t o A N
0
O
A N
t o A N
( 4 p i n s )
0
3
pin.
0
pin again. The conversion result is transmitted to the corresponding AD register i every
0
When AN
, AN
0
Time
0
0
0
0
0
0
0
.
1
1
1
.
1
.
2
2
3
4
7
( 2 )
C o n v e r s i o n r e s u l t i s
t r a n s f e r e d t o A D
pin
c o n v e r s i o n r e g i s t e r 0
0
A/D conversion
8 - b i t r e s o l u t i o n :
8 - b i t r e s o l u t i o n :
2 8 φ
2 8 φ
c y c l e s
A D
1 0 - b i t r e s o l u t i o n :
1 0 - b i t r e s o l u t i o n :
3 3 φ
3 3 φ
c y c l e s
A D
S e t t o " 1 " b y s o f t w a r e
f r e q u e n c y i s l e s s t h a n 1 M H z , s a m p l e a n d h o l d f u n c t i o n c a n n o t b e s e l e c t e d .
A D
C o n v e r s i o n r a t e p e r a n a l o g i n p u t p i n i s 4 9 φ
page 228 of 354
Item
/ d i v i d e d -
T r i g g e r f o r s t a r t i n g
A D
A / D c o n v e r s i o n
Sample & Hold
a n d A N
( 2
0
1
( 3 p i n s ) /
2
pin is completed, the content of the successive
0
are selected
When AN
to AN
1
0
Time
0
0
0
0
0
0
0
0
.
1
1
1
1
1
1
1
.
2
2
2
.
2
3
4
5
5
6
7
( 3 ) C o n s e c u t i v e c o n v e r s i o n
8 - b i t r e s o l u t i o n :
2 8 φ
c y c l e s
A D
c y c l e s
A D
1 0 - b i t r e s o l u t i o n :
3 3 φ
c y c l e s
A D
c y c l e s
A D
Result
Result
c y c l e s f o r 8 - b i t r e s o l u t i o n a n d 5 9 φ
A D
Set-up
O
Software trigger
Trigger by AD
TRG
Not activated
O
A c t i v a t e d
ion start flag to "0".
are selected
When AN
to AN
2
0
Time
0
0
0
0
0
0
0
0
.
1
1
1
1
1
1
1
.
2
2
2
2
2
2
2
.
3
3
3
3
3
4
5
6
6
7
7
8-bit resolution :
28 φ
cycles
AD
10-bit resolution :
33 φ
cycles
AD
C l e a r e d t o " 0 " b y s o f t w a r e
R e s u l t
c y c l e s f o r 1 0 - b i t r e s o l u t i o n .
A D
2. A/D Converter
are selected
3
Time
0
0
.
1
.
2
.
3
4
(4)
A / D
c o n v e r s i o n
i s c o m p l e t e
R e s u l t
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