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(5) Registers related to the address match interrupt
Figure 2.13.2 shows the memory map of address match interrupt-related registers, and Figure 2.13.3
shows address match interrupt-related registers.
Figure 2.13.2. Memory map of address match interrupt-related registers
Address match interrupt enable register
b7
b6
b5
b4
b3
Address match interrupt register i (i = 0, 1)
(b19)
(b16)
(b23)
b7
b3
Figure 2.13.3. Address match interrupt-related registers
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
0009
16
Address match interrupt enable register (AIER)
0010
16
0011
16
Address match interrupt register 0 (RMAD0)
0012
16
0013
16
0014
16
Address match interrupt register 1 (RMAD1)
0015
16
0016
16
b2
b1
b0
Symbol
AIER
Bit symbol
AIER0
AIER1
Nothing is assigned. Write "0" when writing to these bits.
If read, the value is indeterminate.
(b15)
(b8)
b0 b7
b0
b7
Address setting register for address match interrupt
Nothing is assigned. Write "0" when writing to these bits.
If read, the value is indeterminate.
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Address
When reset
0009
XXXXXX00
16
Bit name
Address match interrupt 0
enable bit
Address match interrupt 1
enable bit
Symbol
b0
RMAD0
RMAD1
Function
2. Address Match Interrupt
2
Function
0 : Interrupt disaled
1 : enabled
0 : Interrupt disaled
1 : enabled
Address
When reset
0012
to 0010
X00000
16
16
0016
to 0014
X00000
16
16
Values that can be set
00000
to FFFFF
16
16
R
W
16
16
R
W
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