Renesas M30245 Series User Manual page 73

M30245 Group
U A R T i t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 ( i = 0 t o 3 )
b 7 b 6 b 5 b4 b 3 b 2 b 1 b 0
UARTi transmit/receive control register 1 (i= 0 to 3)
b7 b6 b5 b4
Figure 2.4.5. UARTi-related registers (3)
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
S y m b o l
U i C 0 ( i = 0 t o 3 )
B i t
B i t n a m e
s y m b o l
C L K 0 B R G c o u n t s o u r c e
s e l e c t b i t
C L K 1
C R S C T S / R T S f u n c t i o n
s e l e c t b i t
T X E P T T r a n s m i t r e g i s t e r e m p t y
f l a g
C R D C T S / R T S d i s a b l e b i t
N C H
D a t a o u t p u t s e l e c t b i t
( N o t e 2 )
C K P O L C L K p o l a r i t y s e l e c t b i t
U F O R M T r a n s f e r f o r m a t s e l e c t b i t
( N o t e 3 )
N o t e 1 : S e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o " 0 " .
N o t e 2 : U A R T 2 t r a n s f e r p i n ( T x D
I t c a n n o t b e s e t t o C M O S o u t p u t .
N o t e 3 : O n l y c l o c k s y n c h r o n o u s s e r i a l I / O m o d e a n d 8 - b i t U A R T m o d e a r e v a l i d .
N o t e 4 : T h e c o r r e s p o n d i n g p o r t r e g i s t e r a n d p o r t d i r e c t i o n r e g i s t e r a r e i n v a l i d .
b3 b2 b1 b0
Symbol
UiC1 (i=0 to 3)
Bit Symbol Bit Name
Transmit enable
TE
bit
Transmit buffer
TI
empty flag
Receive enable
RE
bit
Receive
RI
complete flag
UARTi transmit
UiIRS
interrupt cause
select bit
UARTi continuous
UiRRM
receive mode
enable bit
Data logic
UiLCH
select bit
Error signal
UiERE
output enable bit
Note 1: When disabling the error signal output, set the UiERE bit to "0" after setting the
UiMR register.
page 62 of 354
A d d r e s s
0 3 A C , 0 3 6 C , 0 3 3 C , 0 3 2 C
1 6 1 6 1 6 1 6
F u n c t i o n
( D u r i n g c l o c k s y n c h r o n o u s
s e r i a l I / O m o d e )
b 1 b 0
0 0 : f i s s e l e c t e d
1
0 1 : f i s s e l e c t e d
8
1 0 : f i s s e l e c t e d
3 2
1 1 : I n h i b i t e d
V a l i d w h e n b i t 4 = " 0 "
0 : C T S f u n c t i o n i s s e l e c t e d ( N o t e 1 )
1 : R T S f u n c t i o n i s s e l e c t e d ( N o t e 4 )
0 : D a t a p r e s e n t i n t r a n s m i t r e g i s t e r
( d u r i n g t r a n s m i s s i o n )
1 : N o d a t a p r e s e n t i n t r a n s m i t
r e g i s t e r ( t r a n s m i s s i o n c o m p l e t e d )
0 : C T S / R T S f u n c t i o n e n a b l e d
1 : C T S / R T S f u n c t i o n d i s a b l e d
0 : T x D i / S D A i a n d S C L i p i n i s C M O S
o u t p u t
1 : T x D i / S D A i a n d S C L i p i n i s
N - c h a n n e l o p e n d r a i n o u t p u t
0 : T r a n s m i t d a t a i s o u t p u t a t
f a l l i n g e d g e o f t r a n s f e r c l o c k
a n d r e c e i v e d a t a i s i n p u t a t
r i s i n g e d g e
1 : T r a n s m i t d a t a i s o u t p u t a t
r i s i n g e d g e o f t r a n s f e r c l o c k
a n d r e c e i v e d a t a i s i n p u t a t
f a l l i n g e d g e
0 : L S B f i r s t
1 : M S B f i r s t
: P 7 a n d S C L 2 : P 7 ) i s N - c h a n n e l o p e n d r a i n o u t p u t .
2 0 1
Address
03AD , 036D , 033D , 032D
16 16 16 16
Function
(clock synchronous
serial I/O mode)
0 : Transmit disabled
1 : Transmit enabled
0 : Data present in transmit buffer register
1 : No data present in transmit buffer register
0 : Receive disabled
1 : Receive enabled
0 : Data packet in receive buffer register
1 : No data packet in receive buffer register
0 : Transmit buffer empty (TI =1)
1 : Transmit buffer completed ( TXEPT =1)
0 : Continuous receive
mode disabled
Set to "0"
1 : Continuous receive
mode enabled
0 : No reverse
1 : Reverse
Set to "0" 0 : Output disabled
The value is
1 : Output enabled
indeterminate when read.
W h e n r e s e t
, 0 8
1 6
F u n c t i o n
( D u r i n g U A R T m o d e )
b 1 b 0
0 0 : f 0 0 : f 0 0 : f 0 0 : f i s s e l e c t e d i s s e l e c t e d i s s e l e c t e d i s s e l e c t e d
1 1 1 1
0 1 : f 0 1 : f 0 1 : f 0 1 : f i s s e l e c t e d i s s e l e c t e d i s s e l e c t e d i s s e l e c t e d
8 8 8 8
1 0 : f 1 0 : f 1 0 : f 1 0 : f i s s e l e c t e d i s s e l e c t e d i s s e l e c t e d i s s e l e c t e d
3 2 3 2 3 2 3 2
1 1 : I n h i b i t e d 1 1 : I n h i b i t e d 1 1 : I n h i b i t e d 1 1 : I n h i b i t e d
V a l i d w h e n b i t 4 = " 0 "
0 : C T S f u n c t i o n i s s e l e c t e d ( N o t e 1 )
1 : R T S f u n c t i o n i s s e l e c t e d ( N o t e 4 )
0 : D a t a p r e s e n t i n t r a n s m i t r e g i s t e r
( d u r i n g t r a n s m i s s i o n )
1 : N o d a t a p r e s e n t i n t r a n s m i t
r e g i s t e r ( t r a n s m i s s i o n c o m p l e t e d )
0 : C T S / R T S f u n c t i o n e n a b l e d
1 : C T S / R T S f u n c t i o n d i s a b l e d
0 : T x D i / S D A i a n d S C L i p i n i s C M O S
o u t p u t
1 : T x D i / S D A i a n d S C L i p i n i s
N - c h a n n e l o p e n d r a i n o u t p u t
S e t t o " 0 "
0 : L S B f i r s t
1 : M S B f i r s t
When reset
02
16
Function
R W
(UART mode)
(Note 1)
2. UART
R W