Renesas M30245 Series User Manual page 104

M30245 Group
UARTi special mode register 4 (i= 0 to 3)
b7 b6 b5 b4
Interrupt request cause select register
b7 b6 b5 b4
Figure 2.5.7. Serial interface special function-related registers (6)
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
b3 b2 b1 b0
Symbol
UiSMR4 (i=0 to 3) 03A4
Bit Symbol Bit Name
Start condition
STAREQ
generate bit (Note 1)
Restart condition
RSTAREQ
generate bit (Note 1)
Stop condition
STPREQ
generate bit (Note 1)
SCL, SDA output
STSPSEL
select bit
ACKD
ACK data bit
ACK data output
ACKC
enable bit
SCL output stop
SCLHI
enable bit
SWC9
SCL wait output bit 3
Note 1: These bits automatically become "0" when a start condition is generated.
Note 2: This bit is unavailable when SCLi is external clock.
b3 b2 b1 b0
Symbol
IFSR
Bit Symbol
INT0 interrupt polarity
IFSR0
swiching bit
INT1 interrupt polarity
IFSR1
swiching bit
INT2 interrupt polarity
IFSR2
swiching bit
Nothing is assigned.
Write "0" when writing to this bit. The value is indeterminate when read.
Bus collision interrupt
IFSR6
request cause select bit 0
Bus collision interrupt
IFSR7
request cause select bit 1
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Address
, 0364 , 0334 , 0324
16 16 16
Function
0 : Clear
1 : Start
0 : Clear
1 : Start
0 : Clear
1 : Start
0 : Ordinal block
1 : Start/stop condition generate block
0 : ACK
1 : NACK
0 : SI/O data output
1 : ACKD output
0 : Disabled
1 : Enabled
0 : SCL "L" hold disabled
1 : SCL "L" hold enabled (Note 2)
Address When reset
035F , 00
16 16
Bit name
0 : One edge
1 : Two edges
0 : One edge
1 : Two edges
0 : One edge
1 : Two edges
0 : UART0 Bus collision /
Start/stop condition detection /
Trouble error detection
1 : UART2 Bus collision /
Start/stop condition detection /
Trouble error detection
0 : UART1 Bus collision /
Start/stop condition detection /
Trouble error detection
1 : UART3 Bus collision /
Start/stop condition detection /
Trouble error detection
2. Serial Interface Special Function
When reset
00
16 16
R W
Function R W