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M30245 Group
Timing chart
BCLK
HOLD
HLDA
ALE
CSn
ADi
DBi
RD/WR
(1) An "L" level is input to the HOLD pin.
(2) HOLD is detected.
(3) The CPU releases the bus.
(4) An "L" is output to the HLDA pin.
(5) An "H" is input to the HOLD pin.
(6) An "H" is output to the HLDA pin.
(7) The CPU not releases the bus.
(8) The CPU resumes using the bus.
Figure 4.5.1. Example of releasing the external bus
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Indeterminate
(1) (2) (3) (4)
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HiZ
HiZ
HiZ
HiZ
Bus released
(5) (6) (7)
4. External Buses
(8)
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