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M30245 Group
(2) Transfer rate
The divide-by-16 frequency, resulting from division in the bit rate generator (BRG), becomes the trans-
fer rate. The count source for the transfer rate register can be selected from f
from the CLK pin. Clocks f
respectively.
Table 2.4.2. Example of baud rate setting
Baud rate
(bps)
count source
600
1200
2400
4800
9600
14400
19200
28800
31250
(3) An error detection
In UART mode, detected errors are shown in Table 2.4.3.
Table 2.4.3. Error detection
Type of error
Overrun error
F r a m i n g e r r o r
P a r i t y e r r o r
E r r o r - s u m f l a g
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
, f
, f
are derived by dividing the CPU's main clock by 1, 8, and 32
1
8
32
System clock : 16MHz
BRG's
BRG's set value : n
f
207 (CF
8
f
103 (67
8
f
51 (33
8
f
207 (CF
1
f
103 (67
1
f
68 (44
1
f
51 (33
1
f
34 (22
1
f
33 (21
1
Description
• This error occurs when the
serial interface starts receiving
the next data item before
reading the contents of the
UARTi receive buffer register
and receives the bit preceding
the final stop bit of the next
data item.
• The contents of the UARTi
receive buffer register are
undefined.
• The UARTi receive interrupt
request bit does not go to "1".
• This error occurs when the
stop bit falls short of the set
number of stop bits.
• With parity enabled, this error
occurs when the total number
of 1's in character bits and the
parity bit is different from the
specified number.
• This flag turns on when any
error (overrun, framing, or
parity) is detected.
page 56 of 354
Actual time (bps)
)
601
16
)
1202
16
)
2404
16
)
4808
16
)
9615
16
)
14493
16
)
19231
16
)
28571
16
)
31250
16
When the flag turns on
T h e e r r o r i s d e t e c t e d
w h e n d a t a i s
t r a n s f e r r e d f r o m t h e
U A R T i r e c e i v e r e g i s t e r
t o t h e U A R T i r e c e i v e
b u f f e r r e g i s t e r .
, f
, f
, and the input
1
8
32
System clock : 7.3728MHz
BRG's set value : n
Actual time (bps)
95 (5F
)
16
47 (2F
)
16
23 (17
)
16
95 (5F
)
16
47 (2F
)
16
31 (1F
)
16
23 (17
)
16
15 (F
)
16
How to clear the flag
• S e t t h e s e r i a l I / O m o d e s e l e c t
b i t s t o " 0 0 0
" .
2
• S e t t h e r e c e i v e e n a b l e b i t t o
" 0 " .
• Set the serial I/O mode select
bits to "000
".
2
• Set the receive enable bit to
"0".
• Read the lower-order byte of
the UARTi receive buffer
register.
• W h e n a l l e r r o r ( o v e r r u n ,
f r a m i n g , a n d p a r i t y ) a r e
r e m o v e d , t h e f l a g i s c l e a r e d .
2. UART
600
1200
2400
4800
9600
14400
19200
28800
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