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M30245 Group
USB endpoint x(x=0 to 4) OUT FIFO data register
Endpoints 0 to 4 respectively have their OUT FIFOs. When data are received from the host PC, read
the receive data from these registers. Access these registers in word cycle or byte cycle to the lower
byte.
The configuration of USB x(x=0~4) OUT FIFO data register is shown in Figure 2.8.13.
USB Endpoint x OUT FIFO Data register
(b15)
b7
Figure 2.8.13. USB x(x=0~4) OUT FIFO data register
The endpoint x IN/OUT FIFO mapping is shown in Figure 2.8.14.
Endpoint FIFO
3328 bytes
Endpoint 0
IN FIFO:
OUT FIFO: 128 bytes
Figure 2.8.14. Endpoint x IN/OUT FIFO mapping
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
(b8)
b0
b7
b0
64 bytes
64 bytes
128 bytes,
256 bytes
page 142 of 354
Symbol
EPxO (x = 0 - 4)
02E2
02EE
Bit Symbol
Bit Name
EP0 OUT FIFO Data
DATA_15-0
Note 1: Writing to this register might cause a system error.
Note 2: Read only from this register with a Word command or a Byte command to the lower 8
bits. Do not read a byte of data from the upper 8 bits. (b8 - b15)
This area is allocated for IN/OUT FIFOs of the endpoint 1 to 4.
The FIFO size and start position can be specified for every 64-byte by
USB EPx IN FIFO configuration register and USB EPx OUT FIFO configuration register.
2. USB function
Address
When reset
, 02E6
, 02EA
,
N/A
16
16
16
, 02F2
16
16
Function
Read receive data
from this register
R W
O X
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