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M30245 Group
Frequency Synthesizer Control register
b7
b6
b5
b4
b3
b2
0 0
Frequency Synthesizer Clock Control register
b7
b6
b5
b4
b3
b2
0
0
0
0 0
0
Figure 2.7.3. Frequency synthesizer registers (1)
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
b1
b0
Symbol
FSC
Bit Symbol
FSE
Frequency synthesizer enable bit
VCO0
VCO gain control bit
VC01
Reserved bit
CHG0
LPF current control bit (Note 2)
CHG1
Frequency synthesizer lock status bit
LS
Note 1: Recommended.
Note 2: Bits 6 and 5 are set to (bit 6,bit 5)=(1,1) at reset. When using the frequency synthesizer,
we recommend to set to (bit 6,bit 5)=(1,0).
b1
b0
Symbol
FSCCR
Bit Symbol
Clock source selection
FSCCR0
Reserved
FCCR4
Divide-by-3 option
Reserved
page 122 of 354
Address
03DC
16
Bit Name
0 : Disabled
1 : Enabled
b2 b1
0 0 : Lowest gain
0 1 : Low gain
1 0 : High gain (Note 1)
1 1 : Highest gain
b6 b5
0 0 : Disabled
0 1 : Low current
1 0 : Medium current (Note 1)
1 1 : High current
0 : Unlocked
1 : Locked
Address
03DB
16
Bit Name
0 : Xin
1 : f
Must always be set to "0"
0 : Normal
1 : Divide-by-3
Must always be set to "0"
2. Frequency synthesizer (PLL)
When reset
01100000
2
Function
O
O
O
Must always be set to "0"
When reset
00000000
2
Function
R W
O
SYN
O
O
O
R W
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
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