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M30245 Group
I n i t i a l c o n d i t i o n
b 7
1
b7
0
0
0
b7
0
0
0
S e t t i n g i n t e r r u p t e x c e p t s t o p m o d e c a n c e l
n t e r r u p t c o n t r o l r e g i s t e r S i R I C ( i = 0 , 2 , 3 ) [ A d d r e s s 0 0 4 A
I
b7
0
0
Canceling protect
b 7
0
S e t t i n g o p e r a t i o n c l o c k a f t e r r e t u r n i n g f r o m s t o p m o d e
( W h e n o p e r a t i n g w i t h X
b 7
0
0
0
As this register becomes setting mentioned above when
operating with X
(count source of BCLK is X
IN
the user does not need to set it again.
When operating with X
to "0" before setting system clock select bit to "0". The both
bits cannot be set at the same time.
Figure 3.8.3. Set-up procedure of controlling power using stop mode (1)
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
P u l l - u p c o n t r o l r e g i s t e r 2
b 0
[ A d d r e s s 0 3 F E
]
1 6
P U R 2
P 1 0
t o P 1 0
p u l l e d h i g h
0
3
P o r t P 1 0 d i r e c t i o n r e g i s t e r
b 0
[ A d d r e s s 0 3 F 6
]
1 6
0
P D 0
K e y s c a n i n p u t p o r t
P o r t P 0 r e g i s t e r
b 0
[ A d d r e s s 0 3 E 0
]
0
1 6
P 0
K e y s c a n d a t a
, 0 0 4 2
1 6
S 1 3 B C N I C
[ A d d r e s s 0 0 4 3
]
1 6
T A i I C ( i = 0 t o 4 ) [ A d d r e s s 0 0 5 4
, 0 0 4 5
1 6
E P 0 I C
[ A d d r e s s 0 0 4 6
]
1 6
A D I C
[ A d d r e s s 0 0 4 B
]
1 6
D M i I C ( i = 0 t o 3 ) [ A d d r e s s 0 0 4 C
1 6
S i T I C ( i = 0 t o 3 ) [ A d d r e s s 0 0 5 3
, 0 0 5 1
1 6
S U S P I C
[ A d d r e s s 0 0 5 6
]
1 6
R S M I C
[ A d d r e s s 0 0 5 8
]
1 6
R S T I C
[ A d d r e s s 0 0 5 A
]
1 6
S O F I C
[ A d d r e s s 0 0 5 B
]
1 6
V B D I C
[ A d d r e s s 0 0 5 C
1 6
U S B F I C
[ A d d r e s s 0 0 5 D
1 6
b0
0
I n t e r r u p t p r i o r i t y l e v e l s e l e c t b i t
0 0 0 : I n t e r r u p t d i s a b l e d
b 0
Protect register [Address 000A
16
1
PRCR
Enables writing to system clock control registers 0 and 1 (addresses 0006
and frequency synthesizer registers (addresses 03DB
1 : Write-enabled
a f t e r r e t u r n i n g )
I N
System clock control register 0
b 0
0
CM0
[Address 0006
]
16
Reserved bit
Must always be set to "0"
M a i n c l o c k ( X
- X
) s t o p b i t
I N
O U T
O n
S y s t e m c l o c k s e l e c t b i t
X
, X
I N
O U T
),
IN
, set main clock (X
-X
) stop bit
CIN
IN
OUT
C o n t i n u e d t o t h e n e x t p a g e
page 323 of 354
M a i n
b7
1
1
b7
0
Processor interrupt priority level (IPL) = 0
Interrupt enable flag (I) =0
, 0 0 5 5
]
1 6
1 6
, 0 0 4 7
, 0 0 5 7
, 0 0 5 9
]
1 6
1 6
1 6
1 6
, 0 0 4 E
, 0 0 5 0
, 0 0 5 2
]
1 6
1 6
1 6
, 0 0 4 F
, 0 0 4 D
]
1 6
1 6
1 6
]
]
b7
0
0
0
]
to 03DF
)
16
16
( W h e n o p e r a t i n g w i t h X
b 7
1
1
0
As this register becomes setting mentioned above when operating with X
(count source of BCLK is X
When operating with X
clock select bit to "1". The both bits cannot be set at the same time.
3. Controlling Power Applications
Port P0 direction register
b0
[Address 03E2
]
16
1
1
PD0
K e y s c a n o u t p u t p o r t
K e y i n p u t i n t e r r u p t c o n t r o l r e g i s t e r
b 0
[ A d d r e s s 0 0 4 1
]
1 6
0
1
K U P I C
Interrupt priority level select bit
Set higher value than the present IPL
INTiIC(i=0 to 2) [Address 005F
b0
S1RIC
[Address 0048
0
S02BCNIC
[Address 0049
I n t e r r u p t p r i o r i t y l e v e l s e l e c t b i t
0 0 0 : I n t e r r u p t d i s a b l e d
R e s e r v e d b i t
M u s t a l w a y s b e s e t t o " 0 "
and 0007
)
16
16
a f t e r r e t u r n i n g )
C I N
System clock control register 0
b 0
0
CM0 [Address 0006
]
16
Reserved bit
Must always be set to "0"
Port X
select bit
C
X
-X
generation
CIN
COUT
S y s t e m c l o c k s e l e c t b i t
X
, X
C I N
C O U T
), the user does not need to set it again.
CIN
, set port Xc select bit to "1" before setting system
IN
, 0044
, 005E
]
16
16
16
]
16
]
16
CIN
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