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M30245 Group
UARTi special mode register 1 (i= 0 to 3)
b7
b6
b5
UARTi special mode register 2 (i= 0 to 3)
b7
b6
b5
Figure 2.5.5. Serial interface special function-related registers (4)
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
b4
b3
b2
b1
b0
Symbol
UiSMR (i=0 to 3)
Bit Symbol
2
I
C mode
IICM
select bit
Arbitration lost
ABC
detecting flag
control bit
BBS
Bus busy flag
SCLL sync output
LSYN
enable bit
Bus collision
ABSCS
detect sampling
clock select bit
Auto-clear
function select bit
ACSE
of transmit enable
bit
Transmit start
SSS
condition select
bit
Nothing is assigned. Write "0" when writing to this bit.
The values are indeterminate when read.
Note 1: Only "0" may be written
Note 2: UART0 Timer A3 underflow signal, UART1: Timer A4 underlfow signal,
UART2 :Timer A0 underflow signal.
b4
b3
b2
b1
b0
Symbol
UiSMR2 (i=0 to 3) 03A6
Bit Symbol
2
I
C mode
IICM2
select bit 2
CSC
Clock synchronous bit
SWC
SCL wait output bit
ALS
SDA output stop bit
STC
UARTi initialize bit
SCL Wait
SWC2
output bit 2
SDA output
SDHI
inhibit bit
Nothing is assigned. Write "0" when writing to this bit.
The values are indeterminate when read.
Note 1: These bits are unavailable when SCLi is external clock.
page 91 of 354
Address
03A7
, 0367
, 0337
, 0327
16
16
16
Function
Bit Name
(clock synchronous
serial I/O mode)
0 : Normal mode
2
1 : I
C mode
0 : Update per bit
1 : Update per byte
0 : STOP detected
1 : START detected
0 : Disabled
1 : Enabled
Set to "0"
Set to "0"
Set to "0"
Address
, 0366
, 0336
, 0326
16
16
16
Bit Name
0 : NACK/ACK interrupt (DMA source-ACK)
Transfer to receive buffer at the rising edge
of last bit of receive clock.
Receive interrupt occurs at the rising edge
of last bit of receive clock.
1 : UART transfer/receive interrupt (DMA
source-UART receive)
Transfer to receive buffer at the falling edge
of last bit of receive clock.
Receive interrupt occurs at the falling edge
of last bit of receive clock
0 : Disable
1 : Enable
0 : Disable
1 : Enable
0 : Disable
1 : Enable
0 : Disable
1 : Enable
0 : UARTi clock
1 : 0 output
0 : Disabled
1 : Enabled (high impedance)
2. Serial Interface Special Function
When reset
00
16
16
Function
R W
(UART mode)
Set to "0"
Set to "0"
Set to "0"
Set to "0"
(Note 1)
0 : Rising edge of
transfer clock
1 : Timer Ai underflow
signal (Note 2)
0 : No auto clear function
1 : Auto clear when bus
collision occurs
0 : Ordinary
1 : Falling edge of RxDi
When reset
00
16
16
R W
Function
(Note 1)
(Note 1)
(Note 1)
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