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M30245 Group
Example of wiring
Example of operation
(1) Transmission enabled
Transfer clock
"1"
Transmit
enable bit (TE)
"0"
"1"
Transmit
buffer empty
"0"
flag (Tl)
"H"
CTSi
"L"
CLKi
TxDi
Transmit register
"1"
empty flag
"0"
(TXEPT)
"1"
Transmit
interrupt request
"0"
bit (IR)
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = "0".
• Transmit interrupt cause select bit = "0".
Figure 2.3.5. Operation timing of transmission in clock-synchronous serial I/O mode
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Microcomputer
CLKi
T
Di
X
CTSi
Note : Since T
(2) Confirming CTS
(3) Start transmission Tc
Data is set to UARTi transmit buffer register
Transferred from UARTi transmit buffer register to UARTi transmit register
T
CLK
D
D
D
D
D
D
D
0
1
2
3
4
5
6
page 46 of 354
(Note)
Receiver side IC
D
pin is N-channel open drain,
X
2
this pin needs pull-up resistance.
(4) Transmission is complete
(5) Transmit next data
Stopped pulsing because CTSi = "H"
D
D
D
D
D
D
D
D
7
0
1
2
3
4
5
Cleared to "0" when interrupt request is accepted, or cleared by software
Tc = T
= 2(n + 1) / fi
CLK
fi: frequency of BRGi count source (f
n: value set to BRGi
2. Clock-Synchronous Serial I/O
CLK
R
D
X
Port
Stopped pulsing because
transfer enable bit = "0"
D
D
D
D
D
D
6
7
0
1
2
3
4
, f
, f
)
1
8
32
D
D
D
5
6
7
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