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M30245 Group
(6) USB Receive (Endpoints 1 to 4 OUT): Example
The endpoints 1 to 4 OUT packet fetching routine (in continuous transfer disable) is shown in Figure
2.8.44. In addition to packet fetch process, error flag (OVER_RUN, FORCE_STALL, DATA_ERR)
process is required for every transfer type.
1. Confirming of whether one packet is received in the OUT FIFO:
check the OUT_BUF_STS0 and the OUT_BUF_STS1.
(b15)
b7
0
0
No data set in the OUT FIFO
2. Reading of the number of receive one packet data (Note 1) and
storing it in the RAM_CNT (user definition RAM).
(b15)
b7
0
0
0 0
0
Note 1: The packet data is one buffer data in continuous transfer mode.
3. Reading of receive data equal to receive data count (RAM_CNT) from the OUT FIFO
and storing it in the RAM_DATA (user definition RAM).
(b15)
b7
Note 2: Define the RAM_DATA equal to byte count required for receive.
4. Setting of the CLR_OUT_BUF_RDY bit to "1" and
completion (Note 4) of one packet data (Note 3) fetch.
(b15)
b7
0
0
Note 3: The packet data is one buffer data in continuous transfer mode.
Note 4: When the AUTO_CLR bit is set to "1", the OUT_BU_STS0 and the OUT_BUF_STS1 flags are
automatically updated without setting "1" to the CLR_OUT_BUF_RDY bit when the data count equal to
one packet is read from the OUT FIFO.
Execution of the above 2, 3 and 4 when one more are set in the OUT FIFO
Figure 2.8.44. Endpoint 1 to 4 OUT packet fetching routine
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Process of USB endpoint x OUT packet fetch
(b8)
b0
b7
(b8)
b0
b7
(b8)
b0
b7
Read the reception data and store it in the RAM_DATA
(b8)
b0
b7
1
Completion of packet fetch
page 192 of 354
b0
USB endpoint x OUT control and status register
EPxOCS (x = 1 - 4) [Address 02B6
OUT_BUF_STS0 flag
OUT_BUF_STS1 flag
b1 b0
0 0 : No data set in the OUT buffer
0 1 : Invalid
1 0 : Single buffer mode: Invalid
Double buffer mode: one data set in the OUT buffer
1 1 : Single buffer mode: one data set in the OUT buffer
Double buffer mode: two data set in the OUT buffer
Data set in the OUT FIFO
b0
USB endpoint x OUT write count register
EPxWC (x = 1 - 4) [Address 02BA
Read the number of bytes of reception data and
store it in the RAM_CNT
b0
USB endpoint x OUT FIFO data register
EPxO (x = 0 - 4) [Address 02E2
b0
USB endpoint x OUT control and status register
EPxOCS (x = 1 - 4) [Address 02B6
CLR_OUT_BUF_RDY bit
1 : Updates OUT_BUF_STS0, OUT_BUF_STS1 flags
2. USB function
, 02BE
, 02C6
, 02CE
16
16
16
16
, 02C2
, 02CA
, 02D2
16
16
16
16
, 02E6
, 02EA
, 02EE
, 02F2
16
16
16
16
, 02BE
, 02C6
, 02CE
]
16
16
16
16
]
]
]
16
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