Table of Contents
Advertisement
M30245 Group
Table 2.9.11. Variation of the successive comparison register and Vref while A/D conversion is in
progress (8-bit mode)
A/D converter stopped
1st comparison
n
2nd comparison
3rd comparison
8th comparison
Conversion
complete
Result of A/D conversion
FF
16
FE
16
03
16
02
16
01
16
00
16
V
REF
0
256
V
REF
x 3
2048
Figure 2.9.20. Theoretical A/D conversion characteristics (8-bit mode)
Rev.2.00 Oct 16, 2006
page 234 of 354
REJ09B0340-0200
Successive approximation register
b9
1
0 0 0 0 0 0 0 0 0
1
0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0
9
1st comparison result
1 0 0 0 0 0 0 0
n
n
9
8
2nd comparison result
1 0 0
n
n
n
n
n
n
n
9
8
7
6
5
4
3
n
n
n
n
n
n
n
n
9
8
7
6
5
4
3
2
This data transfers to bit 0 to
bit 7 of AD register i.
V
V
REF
x 1
x 2
256
256
b0
V
REF
[V]
2
V
V
REF
REF
[V]
–
2
2048
V
V
REF
REF
±
–
2
4
V
V
REF
REF
±
±
2
4
V
V
REF
REF
±
±
2
4
0 0
Theoretical A/D conversion
characteristic of general 8-bit
A/D converter
Theoretical A/D conversion
characteristic in the 8-bit mode
V
V
REF
REF
x 4
x 3
256
256
2. A/D Converter
V
change
ref
V
REF
n
= 1
+
9
V
4
REF
[V]
V
REF
2048
n
= 0
–
9
4
n
= 1
V
V
8
REF
REF
[V]
–
8
2048
n
= 0
8
V
V
V
REF
REF
± ...... ±
–
2048
8
256
V
REF
REF
x 254
x 255
256
Analog input voltage
V
REF
+
8
V
REF
–
8
REF
[V]
V
REF
Advertisement
Table of Contents
