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M30245 Group
0 0 0 0 0
1 6
0 0 4 0 0
1 6
X X X X X
1 6
YYYYY
16
FFFFF
16
• M e m o r y e x p a n s i o n m o d e a n d m i c r o p r o c e s s o r e x a m p l e s a p p l y w i t h t h e f o l l o w i n g s e t t i n g s :
CS0 = "1"(CS0 output enabled)
CS3 = "1"(CS3 output enabled)
CS0W = "0" (with CS0 wait)
CS3W = "1" (without CS3 wait)
CSE0W = "01
M e m o r y e x p a n s i o n m o d e
00000
16
SFR area
0 0 4 0 0
1 6
I n t e r n a l R A M a r e a
X X X X X
1 6
Internal area reserved
04000
16
C S 3 e x t e r n a l a r e a
0 8 0 0 0
1 6
2 8 0 0 0
1 6
3 0 0 0 0
1 6
CS0 external area
D 0 0 0 0
1 6
I n t e r n a l a r e a r e s e r v e d
Y Y Y Y Y
1 6
I n t e r n a l R O M a r e a
FFFFF
16
Figure 4.4.3. Relation of processor mode and the wait bit (CSiW, CSiEW)
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
S i n g l e - c h i p m o d e
S F R a r e a
I n t e r n a l R A M a r e a
Internal ROM area
" (CS0: 2-wait expansion)
2
BCLK × 2
BCLK × 1
Read BCLK × 1
Write BCLK × 2
BCLK × 3
BCLK × 1
page 344 of 354
BCLK × 2
BCLK × 1
Type No.
BCLK × 1
M30245FCGP
M30245MC-XXXGP
M30245M8-XXXGP
Microprocessor mode
00000
16
00400
16
I n t e r n a l R A M a r e a
XXXXX
16
I n t e r n a l a r e a r e s e r v e d
04000
16
CS3 external area
0 8 0 0 0
1 6
28000
16
30000
16
CS0 external area
FFFFF
16
4. External Buses
Address XXXXX
Address YYYYY
16
02BFF
E0000
16
16
02BFF
E 0 0 0 0
16
1 6
017FF
F0000
16
16
B C L K × 2
SFR area
BCLK × 1
Read BCLK × 1
Write BCLK × 2
B C L K × 3
16
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