Table of Contents
Advertisement
M30245 Group
The interrupt enable flag (I flag), the interrupt request bit, the interrupt priority select bit, and the IPL
are independent, and they are not affected by one another.
Table 2.15.1. Settings of interrupt priority levels
Interrupt priority
level select bit
b2 b1 b0
0
0
0
Level 0 (interrupt disabled)
Level 1
0
0
1
0
1
0
Level 2
0
1
1
Level 3
1
0
0
Level 4
1
0
1
Level 5
1
1
0
Level 6
1
1
1
Level 7
When either the IPL or the interrupt priority level is changed, the new level is reflected to the interrupt
in the following timing:
• When changing the IPL using the REIT instruction, the reflection takes effect as of the instruction
that is executed in 2 clock cycles after the last clock cycle in volved in the REIT instruction.
• When changing the IPL using either the POPC, LDC or LDIPL instruction, the reflection takes
effect as of the instruction that is executed in 3 cycles after the last clock cycle involved in the
instruction used.
• When changing the interrupt priority level using the MOV or similar instruction, the reflection takes
effect as of the instruction that is executed in 2 clock cycles after the last clock cycle involved in
the instruction used.
(5) Interrupt Priority
If there are two or more interrupt requests occurring at a point in time within a single sampling (check-
ing whether interrupt requests are made), the interrupt assigned a higher priority is accepted.
Assign an arbitrary priority to maskable interrupts (peripheral I/O interrupts) using the interrupt priority
level select bit. If the same interrupt priority level is assigned, however, the interrupt assigned a higher
hardware priority is accepted.
Priorities of the special interrupts, such as Reset (dealt with as an interrupt assigned the highest
priority), watchdog timer interrupt, etc. are regulated by hardware.
Figure 2.15.4 shows the priorities of hardware interrupts.
Software interrupts are not affected by the interrupt priority. If an instruction is executed, control
branches invariably to the interrupt routine.
_______
________
Reset > NMI > DBC > Watchdog timer > Peripheral I/O > Single step > Address match
Figure 2.15.4. Hardware interrupts priorities
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Interrupt priority
Priority
level
order
Low
High
page 270 of 354
Table 2.15.2. Interrupt levels enabled according
to the contents of the IPL
IPL
IPL
IPL
IPL
2
1
0
0
0
0
Interrupt levels 1 and above are enabled
0
0
1
Interrupt levels 2 and above are enabled
0
1
0
Interrupt levels 3 and above are enabled
0
1
1
Interrupt levels 4 and above are enabled
1
0
0
Interrupt levels 5 and above are enabled
1
0
1
Interrupt levels 6 and above are enabled
1
1
0
Interrupt levels 7 and above are enabled
1
1
1
All maskable interrupts are disabled
2. Multiple Interrupts
Enabled interrupt priority levels
Advertisement
Table of Contents
