Renesas M30245 Series User Manual page 54

M30245 Group
UARTi bit rate generator (o=0 to 3) (Note 1, 2)
b7
U A R T i t r a n s m i t / r e c e i v e m o d e r e g i s t e r ( i = 0 t o 3 )
b 7 b 6 b 5 b 4 b 3 b 2
Figure 2.3.3. Serial I/O-related registers (2)
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
b0
Assuming that set value = n, BRGi divides the count source by
n + 1
Note 1: Use MOV instruction to write to this register.
Note 2: Write a value to this register while transmit/receive halts.
S y m b o l
U 0 M R
b 1 b 0
U 1 M R
U 2 M R
U 3 M R
B i t
B i t n a m e
s y m b o l
S M D 0
S e r i a l I / O m o d e s e l e c t b i t
S M D 1
SMD2
Internal/external clock
CKDIR
select bit
STPS
Stop bit length select bit
P R Y
O d d / e v e n p a r i t y s e l e c t b i t
P R Y E
P a r i t y e n a b l e b i t
TxD, RxD input/output
SLEP
polarity switch bit (Note 2)
2
Note 1: When I C bus interface mode is selected, set the port direction register for the corresponding port
(SCLi) to 0, or the port direction register to 1 and the port data register to 1. When a mode other than
serial I/O mode is selected, set the port direction register for the corresponding port (CLKi) to 0.
Note 2: Normally set to "0".
Note 3: Set the RxDi pin's port direction register to "0" when receiving.
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Symbol Address When reset
U0BRG 03A9 Indeterminate
16
U1BRG 0369 Indeterminate
16
U2BRG 0339 Indeterminate
16
U3BRG 0329 Indeterminate
16
Function
A d d r e s s W h e n r e s e t
0 3 A 8 0 0
1 6 1 6
0 3 6 8 0 0
1 6 1 6
0 3 3 8 0 0
1 6 1 6
0 3 2 8 0 0
1 6 1 6
F u n c t i o n
( D u r i n g c l o c k s y n c h r o n o u s
s e r i a l I / O m o d e )
M u s t b e f i x e d t o 0 0 1
b2 b1 b0
( N o t e 3 )
0 0 0 : S e r i a l I / O i n v a l i d
0 1 0 : S e r i a l I / O m o d e
2
0 1 1 : I C m o d e
Inhibited except in cases
listed above
0 : Internal clock
1 : External clock (Note 1)
Invalid
Invalid
Invalid
0 : Normal
1 : Reversed
2. Clock-Synchronous Serial I/O
R W
Values that can be set
00 to FF
16 16
Function
(During UART mode)
b2 b1 b0
1 0 0 : T r a n s f e r d a t a 7 b i t s l o n g
1 0 1 : T r a n s f e r d a t a 8 b i t s l o n g
1 1 0 : T r a n s f e r d a t a 9 b i t s l o n g
Inhibited except in cases
listed above
0 : Internal clock
1 : External clock (Note 1)
0 : One stop bit
1 : Two stop bits
V a l i d w h e n b i t 6 = " 1 "
0 : O d d p a r i t y
1 : E v e n p a r i t y
0 : P a r i t y d i s a b l e d
1 : P a r i t y e n a b l e d
R W