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M30245 Group
(4) Output enable time [ta(OE)]
Output enable time [ta(OE)] must satisfy the following conditional expressions:
(a) Vcc = 3.0 to 3.6 V
• With the Wait option cleared
9
ta(OE) < 10
• With the Wait option selected
ta(OE) < (m+0.5) × 10
(m = "1" when 1 wait selected, "m = 2" when 2 waits selected, and "m = 3" when 3 waits selected)
(5) Data setup time [tsu(D)]
Data setup time [tsu(D)] must satisfy the following conditional expressions:
(a) Vcc = 3.0 to 3.6 V
• PM16 = 0 (WR width normal)
tsu(D) < (n – 0.5) × 10
• PM16 = 1 (WR width expanded)
tsu(D) < n × 10
*40(ns) = td(BCLK – DB) – th(BCLK – WR)
= (data output delay time) – (WR signal output hold time)
(n = 1 (no wait), n = 2 (1 wait), n = 3 (2 waits), n = 4 (3 waits))
4000
3920
3500
3000
2920
2500
2000
1920
1920
1500
1420
1000
920
920
500
420
0
1
2
Figure 4.4.1. Relation between the frequency of BCLK and memory (1)
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
/(f(BCLK) × 2) – 60(ns) = tac1(RD-DB)
9
/f(BCLK) – 60(ns) = tac2(RD-DB)
9
/f(BCLK) – 40(ns) = td(DB – WR)
9
/f(BCLK) – 40((ns) = td(DB – WR)
1253
920
920
720
670
587
587
520
420
420
320
253
253
170
120
87
3
4
5
6
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Access time
491
420
364
349
320
295
253
220
206
170
142
120
63
45
31
20
7
8
9
10
11
MHz
4. External Buses
Without wait
1 wait
2 waits
3 waits
284
253
228
206
193
187
170
151
134
120
102
87
74
63
53
11
3
-3
-9
-13
12
13
14
15
170
108
45
-18
16
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