ST STM32G4 Series Reference Manual page 452

Extended interrupts and events controller (EXTI)
15.5.3 Rising trigger selection register 1 (EXTI_RTSR1)
Address offset: 0x08
Reset value: 0x0000 0000
31 30 29
RT31 RT30 RT29 Res.
rw rw rw
15 14 13
RT15 RT14 RT13 RT12
rw rw rw
Bits 31:29 RTx: Rising trigger event configuration bit of line x (x = 31 to 29)
Bits 28:23 Reserved, must be kept at reset value.
Bits 22:19 RTx: Rising trigger event configuration bit of line x (x = 22 to 19)
Bits 17:0 RTx: Rising trigger event configuration bit of line x (x = 17 to 0)
Note: The configurable wakeup lines are edge-triggered. No glitch must be generated on these
lines. If a rising edge on a configurable interrupt line occurs during a write operation in the
EXTI_RTSR register, the pending bit is not set.
Rising and falling edge triggers can be set for the same interrupt line. In this case, both
generate a trigger condition.
15.5.4 Falling trigger selection register 1 (EXTI_FTSR1)
Address offset: 0x0C
Reset value: 0x0000 0000
31 30 29
FT31 FT30 FT29 Res.
rw rw rw
15 14 13
FT15 FT14 FT13 FT12
rw rw rw
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28 27 26 25
Res. Res. Res.
12 11 10 9
RT11 RT10 RT9
rw rw rw rw
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
Bit 18 Reserved, must be kept at reset value.
0: Rising trigger disabled (for Event and Interrupt) for input line
1: Rising trigger enabled (for Event and Interrupt) for input line
28 27 26 25
Res. Res. Res.
12 11 10 9
FT11 FT10 FT9
rw rw rw rw
24 23 22
Res. Res. RT22 RT21
rw
8 7 6
RT8 RT7 RT6
rw rw rw
24 23 22
Res. Res. FT22 FT21
rw
8 7 6
FT8 FT7 FT6
rw rw rw
RM0440 Rev 4
21 20 19 18
RT20 RT19 Res.
rw rw rw
5 4 3 2
RT5 RT4 RT3 RT2
rw rw rw rw
21 20 19 18
FT20 FT19 Res.
rw rw rw
5 4 3 2
FT5 FT4 FT3 FT2
rw rw rw rw
RM0440
17 16
RT17 RT16
rw rw
1 0
RT1 RT0
rw rw
17 16
FT17 FT16
rw rw
1 0
FT1 FT0
rw rw