Clock Sources - Atmel ATtiny25 Manual

6.2

Clock Sources

7598H–AVR–07/09
Figure 6-2. PCK Clocking System
OSCCAL
PLLE
RC OSCILLATOR
8.0 MHz / 6.4 MHz
XTAL1
OSCILLATORS
XTAL2
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Table 6-1. Device Clocking Options Select
Device Clocking Option
External Clock
PLL Clock
Calibrated Internal RC Oscillator 8.0 MHz
Watchdog Oscillator 128 kHz
External Low-frequency Crystal
External Crystal/Ceramic Resonator
Reserved
Note: 1. For all fuses "1" means unprogrammed while "0" means programmed.
The various choices for each clocking option is given in the following sections. When the CPU
wakes up from Power-down or Power-save, the selected clock source is used to time the
start-up, ensuring stable Oscillator operation before instruction execution starts. When the CPU
starts from reset, there is an additional delay allowing the power to reach a stable level before
commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of
the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in
6-2.
PLLCK & CKSEL FUSES
Lock
Detector
PLL
8x / 4x
DIVIDE
BY 4
(1)
ATtiny25/45/85
CLKPS3..0
PLOCK
PCK
64 / 25.6 MHz
SYSTEM
System
CLOCK
Clock
Prescaler
CKSEL3..0
0000
0001
0010
0100
0110
1000-1111
0101, 0111, 0011
Table
23