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7.2
Reset Path
The reset signal is named NRST. It is an open drain path that connects the following together:
AT91CAP9 chip NRST pin (provides an integrated debouncing system)
ICE connector
Memory extension/EBI connector J3
NRST push button BP2
FPGA (standard IO pin AK17)
Motherboard
7.3
Clocking Paths
The AT91CAP9 and the FPGA devices do not share common clocking sources. The only synchroniza-
tion that exists between the two is integrated in the MPIO bus signaling.
7.3.1
AT91CAP9 Clock Sources
On-board 12 MHz quartz
On-board 32768 Hz quartz
Note that the AT91CAP9 chip has integrated PLLs, one being 480 MHz fixed, the two others being con-
figurable and for internal AT91CAP9 chip use only.
7.3.2
FPGA Clock Sources
On-board 12 MHz oscillator, connected to pin T3 (CLK11p)
User clock connector, SMB format, connected to pin T4 (CLK11n)
7.4
Power Supply Circuitry
The AT91CAP9A-DKZ board derives most of the necessary voltages from the motherboard connectors.
Some service voltage sources are regenerated on board.
Please look at the appended schematics:
paths.
7.5
Memory
System memory resources are provided via extension boards in SODIMM-144 format.
There is one each for the AT91CAP9 and the FPGA chips. These connections are labeled "EBI", named
after the Atmel standard "External Bus Interface".
Note that the bus voltage of each of these extensions is automatically customizable:
An adjustable regulator located on the mezzanine board, provides the bus voltage. This voltage
powers both the VCCO of the memory boards and the VCCO of the AT91CAP9 (or the FPGA).
A resistor, deported on the memory board, adjusts that VCCO voltage in function of the memory
components that are mounted on the memory board, so that the AT91CAP9 (or FPGA) busses adapt
automatically to it.
7-4
6321B–CAP–02-Jul-07
Section 16,
sheets 1, 5, 9 and 10 for in-depth details on power
AT91CAP9A-DK Development Kit User Guide
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