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DDR2 Memory Controller Registers
4.10 Interrupt Mask Clear Register (IMCR)
The interrupt mask clear register (IMCR) disables the DDR2 memory controller interrupt. Once an interrupt
is enabled, it may be disabled by writing a 1 to the IMCR bit. The IMCR is shown in
described in
Table
Note:
If the LTMCLR bit in IMCR is set concurrently with the LTMSET bit in the interrupt mask set
register (IMSR), the interrupt is not enabled and neither bit is set to 1.
31
15
LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing 0 has no effect); -n = value after reset
Bit
Field
Value
31-3
Reserved
0
2
LTMCLR
0
1
1-0
Reserved
0
52
DDR2 Memory Controller
34.
Figure 28. Interrupt Mask Clear Register (IMCR)
Reserved
R-0
Table 34. Interrupt Mask Clear Register (IMCR) Field Descriptions
Description
Reserved
Line trap interrupt clear. Write a 1 to clear LTMCLR and the LTMSET bit in the interrupt mask set
register (IMSR); a write of 0 has no effect.
Line trap interrupt is not enabled.
Line trap interrupt is enabled; a write of 1 to the LTMSET bit in IMSR occurred.
Reserved
Reserved
R-0
www.ti.com
Figure 28
and
16
3
2
1
0
LTMCLR
Reserved
R/W1C-0
R-0
SPRUEM4A – November 2007
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