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GPIO Registers
5.1.12 Video Port Pin Interrupt Clear Register (PICLR)
PICLR is an alias of the video port pin interrupt status register (PISTAT) for writes only. Writing a 1 to a bit
of PICLR clears the corresponding bit in PISTAT. Writing a 0 has no effect. Register reads return all 0s.
The video port pin interrupt clear register (PICLR) is shown in
31
23
22
Reserved
PICLR22
R-0
W-0
15
14
PICLR15
PICLR14
W-0
W-0
7
6
PICLR7
PICLR6
W-0
W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 5-13. Video Port Pin Interrupt Clear Register (PICLR) Field Descriptions
(1)
Bit
field
symval
31-23 Reserved
-
22
PICLR22
OF(value)
DEFAULT
NONE
VCTL3CLR
21
PICLR21
OF(value)
DEFAULT
NONE
VCTL2CLR
20
PICLR20
OF(value)
DEFAULT
NONE
VCTL1CLR
19-2
PICLR[19-2]
OF(value)
DEFAULT
NONE
VDATAnCLR
(1)
For CSL implementation, use the notation VP_PICLR_PICLRn_symval
166
General-Purpose I/O Operation
Figure 5-12. Video Port Pin Interrupt Clear Register (PICLR)
Reserved
21
20
PICLR21
PICLR20
W-0
W-0
13
12
PICLR13
PICLR12
W-0
W-0
5
4
PICLR5
PICLR4
W-0
W-0
(1)
Value Description
0
Reserved. The reserved bit location is always read as 0. A value written to this field
has no effect.
Allows PISTAT22 bit to be cleared to a logic low.
0
No effect.
1
Clears PISTAT22 (VCTL3) bit to 0.
Allows PISTAT21 bit to be cleared to a logic low.
0
No effect.
1
Clears PISTAT21 (VCTL2) bit to 0.
Allows PISTAT20 bit to be cleared to a logic low.
0
No effect.
1
Clears PISTAT20 (VCTL1) bit to 0.
Allows PISTAT[19-2] bit to be cleared to a logic low.
0
No effect.
1
Clears PISTAT[n] (VDATA[n]) bit to 0.
Figure 5-12
R-0
19
18
PICLR19
PICLR18
W-0
W-0
11
10
Reserved
Reserved
R-0
R-0
3
2
PICLR3
PICLR2
W-0
W-0
www.ti.com
and described in
Table
5-13.
24
17
16
PICLR17
PICLR16
W-0
W-0
9
8
PICLR9
PICLR8
W-0
W-0
1
0
Reserved
Reserved
R-0
R-0
SPRUEM1 – May 2007
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