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Programmer's Model
3.2
Register descriptions
3.2.1
Identification Register, r0
3-4
This section describes the ETB11 registers:
•
Identification Register, r0
•
RAM Depth Register, r1 on page 3-5
•
RAM Width Register, r2 on page 3-5
•
Status Register, r3 on page 3-6
•
RAM Data Register, r4 on page 3-7
•
RAM Read Pointer Register, r5 on page 3-7
•
RAM Write Pointer Register, r6 on page 3-8
•
Trigger Counter Register, r7 on page 3-9
•
Control Register, r8 on page 3-10.
The Identification Register enables the TAP controller to be identified by Multi-ICE, or
any other run control device. It is a read-only 32-bit register. Table 3-2 describes the
bits.
Bit
Value
number
[31:28]
0x2
[27:12]
0xB900
[11:1]
0x787
[0]
1
For the current implementation the ID value is
tools check the value of bits [27:1] to detect that the ETB11 is present.
Copyright © 2002, 2003 ARM Limited. All rights reserved.
Table 3-2 Identification register description
Description
Version
Part number
Manufacturer identity. This field always indicates ARM as
a manufacturer and cannot be changed to indicate the
silicon manufacturer.
Always 1 as defined by IEEE 1149.1
32'h2B900F0F
. It is recommended that
ARM DDI 0275D
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