Pmu Management Registers; Peripheral Identification Registers - ARM Cortex A9 Technical Reference Manual

11.3

PMU management registers

Register
number
960
961-999
1000
1001
1002-1003
1004
1005
1006
1007-1009
1010
1011
1012-1019
1020- 1023
11.3.1

Peripheral Identification Registers

ARM DDI 0388I
ID073015
The PMU management registers define the standardized set of registers that is implemented by
all CoreSight components. This section describes these registers.
You can access these registers through the APB interface only, using the offset listed in
Table 11-2 when PADDRDBG[12]=1.
Table 11-2 shows the contents of the management registers for the Cortex-A9 PMU.
Offset Name
PMITCTRL
0xF00
-
0xF04-0xF9C
PMCLAIMSET
0xFA0
PMCLAIMCLR
0xFA4
-
0xFA8-0xFBC
PMLAR
0xFB0
PMLSR
0xFB4
PMAUTHSTATUS
0xFB8
-
0xFBC-0xFC4
PMDEVID
0xFC8
PMDEVTYPE
0xFCC
PMPID
0xFD0-0xFEC
PMCID
0xFF0-0xFFC
The Peripheral Identification Registers are read-only registers that provide standard information
required by all components that conform to the ARM Debug interface v5 specification. The
Peripheral Identification Registers are accessible from the Debug APB bus. Only bits [7:0] of
each register are used the remaining bits Read-As-Zero. The values in these registers are fixed.
Table 11-3 shows the register number, offset value, name, type, value, and description that are
associated with each PMU Peripheral Identification Register.
Register
Offset
number
1012
0xFD0
1013
0xFD4
1014
0xFD8
1015
0xFDC
Copyright © 2008-2012 ARM. All rights reserved.
Type Description
RAZ/WI Integration Mode Control Register
RAZ Reserved
RW Claim Tag Set Register
RW Claim Tag Clear Register
RAZ Reserved
WO Lock Access Register
RO Lock Status Register
RO Authentication Status Register
RAZ Reserved
RAZ/WI Device ID Register
RO Device Type Register
RO See Peripheral Identification Registers
RO See Component Identification Registers on page 11-6
Table 11-3 Peripheral Identification Registers
Name Type
PMPID4 RO
PMPID5 RO
PMPID6 RO
PMPID7 RO
Non-Confidential
Performance Monitoring Unit
Table 11-2 PMU management registers
Value Description
Peripheral Identification Register 4
0x04
- Reserved
- Reserved
- Reserved
11-5