Bus Operation For Executing Instructions - Toshiba TLCS-90 Series Data Book

TOSHIBA TMP90C840
3.2.6 Bus operation for executing instructions
The TMP90C840 adopts a pipeline processing method in which it executes
an instruction simultaneous with the next instruction fetch. The
concept of this processing is illustrated in Fig. 3.2 (7).
Address
100 101
Fetch instruc-
I
Execute in-
tion in address
I
struction in
100
I
address 100
102
Fetch instruc-
I
Execute in-
tion in addressl strcution in
101
I
address 101
Fetch instruc-
I
tion in address
I
102
I
Fig. 3.2
(7)
Pipeline Processing
This pipeline processing allows the TMP90C840 to obtain a higher
executing speed than the conventional method that fetches the next
instruction after the previous instruction is executed. The bus
operation for each instruction begins with "fetching a code in the
address that follows the first instruction code", and not with
"fetching the first instruction code". The first instruction code is
fetched when the CPU is execut ing the previous instruction. An
example of this processing is shown in Fig. 3.2 (8).
Address
I
INC A
I
LD B,A
I
ADD A,n
n
DEC H
Execute Execute
I
Execute
I
Execute Execute
CPU INC A LD B,A
I
internal
I
ADD A,n DEC H
I
operation
I
I
,
>'< >'< >'
I
<INC A >'<LD B,A
,
ADD A,n
,
DEC H
,
Bus Bus Bus operation Bus
operation operation
operation
Fig. 3.2 (8) Pipeline Processing and Bus Operation
MPU90-30