Figure 68. Platform Clock Architecture (2 Dimms) - Intel 815 Design Manual

Clocking

Figure 68. Platform Clock Architecture (2 DIMMs)

Clock Synthesizer
132
52
CPU 2_ITP
55
APIC 0
2.5 V
50
CPU 1
49
CPU 0
32
PW RDW N#
29
SEL1
28
SEL0
30
SData
31
SClk
46
SDRAM(0)
Mem ory
45
SDRAM(1)
2 DIM Ms
43
SDRAM(2)
42
SDRAM(3)
40
SDRAM(4)
39
SDRAM(5)
37
SDRAM(6)
36
SDRAM(7)
34
DCLK
3.3 V
7
3V66 0
26
DOT
14.318 MHz
8
3V66 1
1
REF
11
PCI 0 / ICH
25
USB
54
APIC 1
2.5 V
12
PCI 1
3.3 V
13
PCI 2
15
PCI 3
16
PCI 4
18
PCI 5
19
PCI 6
20
PCI 7
ITP
AGP
Data
M ain
Address
Graphics
Control
Dot clock
I/O Controller Hub
SIO
PCI total of 6
devices (µATX )
5 slots + 1 down
®
Intel 815 Chipset Platform Design Guide
Processor
Host unit
Mem ory
GM CH
unit
Hub I/F
32.768 kHz
clk_arch_2DIMM
R