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Philips Semiconductors
Volume 1
The auto-baud interrupts have to be cleared by setting the corresponding U1ACR
ABTOIntClr and ABEOIntEn bits.
Typically the fractional baud-rate generator is disabled (DIVADDVAL = 0) during
auto-baud. However, if the fractional baud-rate generator is enabled (DIVADDVAL > 0), it
is going to impact the measuring of UART1 Rx pin baud-rate, but the value of the U1FDR
register is not going to be modified after rate measurement. Also, when auto-baud is used,
any write to U1DLM and U1DLL registers should be done before U1ACR register write.
The minimum and the maximum baudrates supported by UART1 are function of PCLK,
number of data bits, stop-bits and parity bits.
10.3.16 Auto-baud Modes
When the software is expecting an "AT" command, it configures the UART1 with the
expected character format and sets the U1ACR Start bit. The initial values in the divisor
latches U1DLM and U1DLM don't care. Because of the "A" or "a" ASCII coding
("A" = 0x41, "a" = 0x61), the UART1 Rx pin sensed start bit and the LSB of the expected
character are delimited by two falling edges. When the U1ACR Start bit is set, the
auto-baud protocol will execute the following phases:
User manual
•
The U1IIR ABEOInt interrupt will get set if the interrupt is enabled (U1IER ABEOIntEn
is set and the auto-baud has completed successfully).
× CLK
2 P
≤
ratemin
=
------------------------ -
16 2 15
×
1. On U1ACR Start bit setting, the baud-rate measurement counter is reset and the
UART1 U1RSR is reset. The U1RSR baud rate is switch to the highest rate.
2. A falling edge on UART1 Rx pin triggers the beginning of the start bit. The rate
measuring counter will start counting PCLK cycles optionally pre-scaled by the
fractional baud-rate generator.
3. During the receipt of the start bit, 16 pulses are generated on the RSR baud input with
the frequency of the (fractional baud-rate pre-scaled) UART1 input clock,
guaranteeing the start bit is stored in the U1RSR.
4. During the receipt of the start bit (and the character LSB for mode = 0) the rate
counter will continue incrementing with the pre-scaled UART1 input clock (PCLK).
5. If Mode = 0 then the rate counter will stop on next falling edge of the UART1 Rx pin. If
Mode = 1 then the rate counter will stop on the next rising edge of the UART1 Rx pin.
6. The rate counter is loaded into U1DLM/U1DLL and the baud-rate will be switched to
normal operation. After setting the U1DLM/U1DLL the end of auto-baud interrupt
U1IIR ABEOInt will be set, if enabled. The U1RSR will now continue receiving the
remaining bits of the "A/a" character.
Rev. 01 — 15 August 2005
≤
1
----------------------------------------------------------------------------------------------------------- -
UART
×
(
baudrate
16
2
+
UM10139
Chapter 10: UART1
PCLK
databits
+
paritybits
+
stopbits
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
(6)
=
ratemax
)
129
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