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Philips Semiconductors
Volume 1
Table 19:
PLLC
0
0
1
1
3.8.7 PLL Feed register (PLL0FEED - 0xE01F C08C, PLL1FEED -
0xE01F C0AC)
A correct feed sequence must be written to the PLLFEED register in order for changes to
the PLLCON and PLLCFG registers to take effect. The feed sequence is:
The two writes must be in the correct sequence, and must be consecutive VPB bus
cycles. The latter requirement implies that interrupts must be disabled for the duration of
the PLL feed operation. If either of the feed values is incorrect, or one of the previously
mentioned conditions is not met, any changes to the PLLCON or PLLCFG register will not
become effective.
Table 20:
Bit
7:0
3.8.8 PLL and Power-down mode
Power-down mode automatically turns off and disconnects activated PLL(s). Wakeup from
Power-down mode does not automatically restore the PLL settings, this must be done in
software. Typically, a routine to activate the PLL, wait for lock, and then connect the PLL
can be called at the beginning of any interrupt service routine that might be called due to
the wakeup. It is important not to attempt to restart the PLL by simply feeding it when
execution resumes after a wakeup from Power-down mode. This would enable and
connect the PLL at the same time, before PLL lock is established.
If activity on the USB data lines is not selected to wake up the microcontroller from
Power-down mode (see
0xE01F C144)" on page
turned off and disconnected when Power-down mode is invoked, as described above.
However, in case USBWAKE = 1 and USB_need_clock = 1 it is not possible to go into
Power-down mode and any attempt to set the PD bit will fail, leaving the PLLs in the
current state.
User manual
PLL Control bit combinations
PLLE
PLL Function
0
PLL is turned off and disconnected. The CCLK equals the unmodified clock
input. This combination can not be used in case of the PLL1 since there will be
no 48 MHz clock and the USB can not operate.
1
The PLL is active, but not yet connected. The PLL can be connected after
PLOCK is asserted.
0
Same as 00 combination. This prevents the possibility of the PLL being
connected without also being enabled.
1
The PLL is active and has been connected. CCLK/system clock is sourced
from the PLL0 and the USB clock is sourced from the PLL1.
1. Write the value 0xAA to PLLFEED.
2. Write the value 0x55 to PLLFEED.
PLL Feed register (PLL0FEED - address 0xE01F C08C, PLL1FEED - address
0xE01F C0AC) bit description
Symbol
Description
PLLFEED The PLL feed sequence must be written to this register in order for
PLL configuration and control register changes to take effect.
Section 3.5.3 "Interrupt Wakeup register (INTWAKE -
Rev. 01 — 15 August 2005
22), both the system and the USB PLL will be automatically be
UM10139
Chapter 3: System Control Block
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Reset
value
0x00
32
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