Philips LPC214 Series User Manual page 342

Philips Semiconductors
Volume 1
10.3.4 UART1 Fractional Divider Register (U1FDR -
0xE001 0028) . . . . . . . . . . . . . . . . . . . . . . . . 116
10.3.5 UART1 baudrate calculation . . . . . . . . . . . . . 117
10.3.6 UART1 Interrupt Enable Register (U1IER -
0xE001 0004, when DLAB = 0) . . . . . . . . . . 118
10.3.7 UART1 Interrupt Identification Register (U1IIR -
0xE001 0008, Read Only) . . . . . . . . . . . . . . 119
10.3.8 UART1 FIFO Control Register (U1FCR -
0xE001 0008) . . . . . . . . . . . . . . . . . . . . . . . . 121
10.3.9 UART1 Line Control Register (U1LCR -
0xE001 000C). . . . . . . . . . . . . . . . . . . . . . . . 122
10.3.10 UART1 Modem Control Register (U1MCR -
0xE001 0010), LPC2144/6/8 only . . . . . . . . 123
2
Chapter 11: I C interfaces I
11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
11.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 133
11.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
11.4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 134
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11.5 I C operating modes . . . . . . . . . . . . . . . . . . . 134
11.5.1 Master Transmitter mode . . . . . . . . . . . . . . . 134
11.5.2 Master Receiver mode . . . . . . . . . . . . . . . . . 135
11.5.3 Slave Receiver mode . . . . . . . . . . . . . . . . . . 136
11.5.4 Slave Transmitter mode . . . . . . . . . . . . . . . . 137
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11.6 I C Implementation and operation . . . . . . . . 138
11.6.1 Input filters and output stages . . . . . . . . . . . 138
11.6.2 Address Register, I2ADDR . . . . . . . . . . . . . . 140
11.6.3 Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . 140
11.6.4 Shift register, I2DAT . . . . . . . . . . . . . . . . . . . 140
11.6.5 Arbitration and synchronization logic . . . . . . 140
11.6.6 Serial clock generator . . . . . . . . . . . . . . . . . . 141
11.6.7 Timing and control . . . . . . . . . . . . . . . . . . . . 141
11.6.8 Control register, I2CONSET and I2CONCLR 141
11.6.9 Status decoder and Status register . . . . . . . 142
11.7 Register description . . . . . . . . . . . . . . . . . . . 142
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11.7.1 I C Control Set register (I2CONSET: I2C0,
I2C0CONSET - 0xE001 C000 and I2C1,
I2C1CONSET - 0xE005 C000) . . . . . . . . . . . 143
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11.7.2 I C Control Clear register (I2CONCLR: I2C0,
I2C0CONCLR - 0xE001 C018 and I2C1,
I2C1CONCLR - 0xE005 C018). . . . . . . . . . . 144
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11.7.3 I C Status register (I2STAT: I2C0, I2C0STAT -
0xE001 C004 and I2C1, I2C1STAT -
0xE005 C004). . . . . . . . . . . . . . . . . . . . . . . . 145
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11.7.4 I C Data register (I2DAT:
I2C0, I2C0DAT - 0xE001 C008 and
I2C1, I2C1DAT - 0xE005 C008) . . . . . . . . . . 145
User manual
2 2
C0 and I C1
Rev. 01 - 15 August 2005
Chapter 25: Supplementary information
10.3.11 UART1 Line Status Register (U1LSR -
0xE001 0014, Read Only) . . . . . . . . . . . . . . 125
10.3.12 UART1 Modem Status Register (U1MSR -
0xE001 0018), LPC2144/6/8 only . . . . . . . . 127
10.3.13 UART1 Scratch pad register (U1SCR -
0xE001 001C) . . . . . . . . . . . . . . . . . . . . . . . 127
10.3.14 UART1 Auto-baud Control Register (U1ACR -
0xE001 0020). . . . . . . . . . . . . . . . . . . . . . . . 127
10.3.15 Auto-baud. . . . . . . . . . . . . . . . . . . . . . . . . . . 128
10.3.16 Auto-baud Modes. . . . . . . . . . . . . . . . . . . . . 129
10.3.17 UART1 Transmit Enable Register (U1TER -
0xE001 0030). . . . . . . . . . . . . . . . . . . . . . . . 130
10.4 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 131
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11.7.5 I C Slave Address register (I2ADR: I2C0,
I2C0ADR - 0xE001 C00C and I2C1, I2C1ADR -
address 0xE005 C00C) . . . . . . . . . . . . . . . . 146
2
11.7.6 I C SCL High duty cycle register (I2SCLH: I2C0,
I2C0SCLH - 0xE001 C010 and I2C1, I2C1SCLH -
0xE0015 C010) . . . . . . . . . . . . . . . . . . . . . . 146
2
11.7.7 I C SCL Low duty cycle register (I2SCLL: I2C0 -
I2C0SCLL: 0xE001 C014; I2C1 - I2C1SCLL:
0xE0015 C014) . . . . . . . . . . . . . . . . . . . . . . 146
11.7.8 Selecting the appropriate I
cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
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11.8 Details of I C operating modes . . . . . . . . . . 147
11.8.1 Master Transmitter mode . . . . . . . . . . . . . . . 148
11.8.2 Master Receiver mode . . . . . . . . . . . . . . . . . 148
11.8.3 Slave Receiver mode . . . . . . . . . . . . . . . . . . 149
11.8.4 Slave Transmitter mode . . . . . . . . . . . . . . . . 153
11.8.5 Miscellaneous States . . . . . . . . . . . . . . . . . . 159
11.8.6 I2STAT = 0xF8 . . . . . . . . . . . . . . . . . . . . . . . 159
11.8.7 I2STAT = 0x00 . . . . . . . . . . . . . . . . . . . . . . . 159
11.8.8 Some special cases . . . . . . . . . . . . . . . . . . . 160
11.8.9 Simultaneous repeated START conditions from
two masters . . . . . . . . . . . . . . . . . . . . . . . . . 160
11.8.10 Data transfer after loss of arbitration . . . . . . 160
11.8.11 Forced access to the I
2
11.8.12 I C-bus obstructed by a low level on
SCL or SDA . . . . . . . . . . . . . . . . . . . . . . . . . 161
11.8.13 Bus error . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
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11.8.14 I C State service routines . . . . . . . . . . . . . . 162
11.8.15 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 163
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11.8.16 I C interrupt service . . . . . . . . . . . . . . . . . . . 163
11.8.17 The State service routines . . . . . . . . . . . . . . 163
11.8.18 Adapting State services to an application . . 163
11.9 Software example . . . . . . . . . . . . . . . . . . . . . 163
11.9.1 Initialization routine . . . . . . . . . . . . . . . . . . . 163
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
UM10139
2
C data rate and duty
2
C-bus. . . . . . . . . . . . 160
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