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Philips Semiconductors
Volume 1
Table 27:
Bit
2
3
7:4
3.11 VPB divider
The VPB Divider determines the relationship between the processor clock (CCLK) and the
clock used by peripheral devices (PCLK). The VPB Divider serves two purposes.
The first is to provides peripherals with desired PCLK via VPB bus so that they can
operate at the speed chosen for the ARM processor. In order to achieve this, the VPB bus
may be slowed down to one half or one fourth of the processor clock rate. Because the
VPB bus must work properly at power up (and its timing cannot be altered if it does not
work since the VPB divider control registers reside on the VPB bus), the default condition
at reset is for the VPB bus to run at one quarter speed.
The second purpose of the VPB Divider is to allow power savings when an application
does not require any peripherals to run at the full processor rate.
The connection of the VPB Divider relative to the oscillator and the processor clock is
shown in
remains active (if it was running) during Idle mode.
3.11.1 Register description
Only one register is used to control the VPB Divider.
Table 28:
Name
VPBDIV
[1]
3.11.2 VPBDIV register (VPBDIV - 0xE01F C100)
The VPB Divider register contains two bits, allowing three divider values, as shown in
Table
User manual
Reset Source identification Register (RSIR - address 0xE01F C180) bit description
Symbol Description
WDTR
This bit is set when the Watchdog Timer times out and the WDTRESET
bit in the Watchdog Mode Register is 1. It is cleared by any of the other
sources of Reset.
BODR
This bit is set when the 3.3 V power reaches a level below 2.6 V. If the
V
voltage dips from 3.3 V to 2.5 V and backs up, the BODR bit will be
DD
set to 1. Also, if the V
level above 2.6 V, the BODR will be set to 1, too. This bit is not affected
by External Reset nor Watchdog Reset.
Note: only in case a reset occurs and the bit POR = 0, the BODR bit
indicates if the V
-
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Figure
11. Because the VPB Divider is connected to the PLL output, the PLL
VPB divider register map
Description
Controls the rate of the VPB clock in relation to
the processor clock.
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
29.
Rev. 01 — 15 August 2005
voltage rises continuously from below 1 V to a
DD
voltage was below 2.6 V or not.
DD
UM10139
Chapter 3: System Control Block
Access Reset
Address
[1]
value
R/W
0x00
0xE01F C100
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Reset
value
see text
see text
NA
40
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