Memory Mapping Control Usage Notes; Phase Locked Loop (Pll) - Philips LPC214 Series User Manual

Philips Semiconductors
Volume 1
Table 14:
Bit
1:0
7:2

3.7.2 Memory mapping control usage notes

The Memory Mapping Control simply selects one out of three available sources of data
(sets of 64 bytes each) necessary for handling ARM exceptions (interrupts).
For example, whenever a Software Interrupt request is generated, the ARM core will
always fetch 32-bit data "residing" on 0x0000 0008 see
locations" on page
read/fetch from 0x0000 0008 will provide data stored in 0x4000 0008. In case of
MEMMAP[1:0]=00 (Boot Loader Mode), a read/fetch from 0x0000 0008 will provide data
available also at 0x7FFF E008 (Boot Block remapped from on-chip Bootloader).

3.8 Phase Locked Loop (PLL)

There are two PLL modules in the LPC2141/2/4/6/8 microcontroller. The PLL0 is used to
generate the CCLK clock (system clock) while the PLL1 has to supply the clock for the
USB at the fixed rate of 48 MHz. Structurally these two PLLs are identical with exception
of the PLL interrupt capabilities reserved only for the PLL0.
The PLL0 and PLL1 accept an input clock frequency in the range of 10 MHz to 25 MHz
only. The input frequency is multiplied up the range of 10 MHz to 60 MHz for the CCLK
and 48 MHz for the USB clock using a Current Controlled Oscillators (CCO). The
multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be
higher than 6 on the LPC2141/2/4/6/8 due to the upper frequency limit of the CPU). The
CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the
loop to keep the CCO within its frequency range while the PLL is providing the desired
output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the
output clock. Since the minimum output divider value is 2, it is insured that the PLL output
has a 50% duty cycle. A block diagram of the PLL is shown in
PLL activation is controlled via the PLLCON register. The PLL multiplier and divider values
are controlled by the PLLCFG register. These two registers are protected in order to
prevent accidental alteration of PLL parameters or deactivation of the PLL. Since all chip
operations, including the Watchdog Timer, are dependent on the PLL0 when it is providing
the chip clock, accidental changes to the PLL setup could result in unexpected behavior of
User manual
Memory Mapping control register (MEMMAP - address 0xE01F C040) bit
description
Symbol Value Description
MAP 00 Boot Loader Mode. Interrupt vectors are re-mapped to Boot
Block.
01 User Flash Mode. Interrupt vectors are not re-mapped and
reside in Flash.
10 User RAM Mode. Interrupt vectors are re-mapped to Static
RAM.
11 Reserved. Do not use this option.
Warning: Improper setting of this value may result in incorrect
operation of the device.
- - Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
12. This means that when MEMMAP[1:0]=10 (User RAM Mode), a
Rev. 01 — 15 August 2005
UM10139
Chapter 3: System Control Block
Table 3 "ARM exception vector
Figure 9.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Reset
value
00
NA
27