Transferring The Data; Optimizing Descriptor Fetch - Philips LPC214 Series User Manual

Philips Semiconductors
Volume 1
The full DMA descriptor (4 words) will in turn be fetched from this address pointed by DDP.
The DD will give the details of the transfer to be done. The DMA engine will load its
hardware resources with the information fetched from the DD (start address, DMA count
etc.).
If the 'next_dd_valid' is not set and the DD_retired bit is set the DMA engine will raise the
'NEW_DD_REQUEST' interrupt for this endpoint. It also disables the DMA_ENABLE bit.
UDCA Head
Register
USB
Device
Controller
Fig 53. Finding the DMA descriptor

14.12.3 Transferring the Data

In case of OUT endpoints, the current packet will be read from the EP_RAM by the DMA
Engine and will get transferred to the USB RAM memory locations starting from the
address pointed by 'dma_buffer_start_addr'. In case of IN endpoints, the data will be
fetched from the USB RAM and will be written to the EP_RAM. The
'dma_buffer_start_addr' and 'present_dma_count' will get updated while the transfer
progresses.

14.12.4 Optimizing Descriptor Fetch

A DMA transfer normally involves multiple packet transfers. If a DD once fetched is
equipped to do multiple transfers, the hardware will not fetch DD for all the succeeding
packets. It will do the fetching only if the previous packet transferred on this channel does
not belong to this endpoint. This is on the assumption that the current contents of the
hardware resource and that of the descriptor to be fetched will be the same. In such a
case DMA engine can proceed without fetching the new descriptor if it has not transferred
enough data specified in the 'dma_buffer_length' field of the descriptor. To keep this
information the hardware will have a flag set called 'DMA_PROCEED'.
This flag will be reset after the required number of bytes specified in the
'dma_buffer_length' field is transferred. It is also reset when the software writes into the
EP DMA Disable register. This will give the software control over the reading of DD by the
hardware. Hardware will be forced to read the DD for the next packet. Writing data 0x0
into the EP DMA Disable register will cause only resetting of the DMA_PROCEED flag
without disabling DMA for any endpoint.
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Rev. 01 — 15 August 2005
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Chapter 14: USB Device Controller
USB RAM
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DD-EP31
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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