Philips LPC214 Series User Manual page 333

Philips Semiconductors
Volume 1
bit description . . . . . . . . . . . . . . . . . . . . . . . . .101
Table 105:UART0 interrupt handling . . . . . . . . . . . . . . . .102
Table 106:UART0 FIFO Control Register (U0FCR - address
0xE000 C008) bit description . . . . . . . . . . . . .103
Table 107:UART0 Line Control Register (U0LCR - address
0xE000 C00C) bit description. . . . . . . . . . . . .103
Table 108:UART0 Line Status Register (U0LSR - address
0xE000 C014, read only) bit description. . . . .104
Table 109:UART0 Scratch pad register (U0SCR - address
0xE000 C01C) bit description. . . . . . . . . . . . .105
Table 110:Auto-baud Control Register (U0ACR -
0xE000 C020) bit description . . . . . . . . . . . . .106
Table 111:UART0 Transmit Enable Register (U0TER -
address 0xE000 C030) bit description . . . . . .107
Table 112:UART1 pin description . . . . . . . . . . . . . . . . . .112
Table 113:UART1 register map . . . . . . . . . . . . . . . . . . .114
Table 114:UART1 Receiver Buffer Register (U1RBR -
address 0xE001 0000, when DLAB = 0 Read
Only) bit description . . . . . . . . . . . . . . . . . . . .115
Table 115:UART1 Transmitter Holding Register (U1THR -
address 0xE001 0000, when DLAB = 0 Write
Only) bit description . . . . . . . . . . . . . . . . . . . .115
Table 116:UART1 Divisor Latch LSB register (U1DLL -
address 0xE001 0000, when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Table 117:UART1 Divisor Latch MSB register (U1DLM -
address 0xE001 0004, when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .116
Table 118:UART1 Fractional Divider Register (U1FDR -
address 0xE001 0028) bit description . . . . . .116
Table 119:Baudrates available when using 20 MHz
peripheral clock (PCLK = 20 MHz) . . . . . . . . .117
Table 120:UART1 Interrupt Enable Register (U1IER -
address 0xE001 0004, when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .118
Table 121:UART1 Interrupt Identification Register
(U1IIR - address 0xE001 0008, read only)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .119
Table 122:UART1 interrupt handling . . . . . . . . . . . . . . . .121
Table 123:UART1 FIFO Control Register (U1FCR - address
0xE001 0008) bit description . . . . . . . . . . . . .122
Table 124:UART1 Line Control Register (U1LCR - address
0xE001 000C) bit description . . . . . . . . . . . . .122
Table 125:UART1 Modem Control Register (U1MCR -
address 0xE001 0010), LPC2144/6/8 only bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .123
Table 126:Modem status interrupt generation . . . . . . . . .125
Table 127:UART1 Line Status Register (U1LSR - address
0xE001 0014, read only) bit description . . . . .125
Table 128:UART1 Modem Status Register (U1MSR -
address 0xE001 0018), LPC2144/6/8 only bit
User manual
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 129:UART1 Scratch pad register (U1SCR - address
0xE001 0014) bit description . . . . . . . . . . . . . 127
Table 130:Auto-baud Control Register (U1ACR -
0xE001 0020) bit description . . . . . . . . . . . . . 128
Table 131:UART1 Transmit Enable Register (U1TER -
address 0xE001 0030) bit description . . . . . . 131
2
Table 132:I
Table 133:I2C0CONSET and I2C1CONSET used to
configure Master mode . . . . . . . . . . . . . . . . . 135
Table 134:I2C0CONSET and I2C1CONSET used to
configure Slave mode . . . . . . . . . . . . . . . . . . 136
2
Table 135:I
2
Table 136:I
I2C0CONSET - address 0xE001 C000 and I2C1,
I2C1CONSET - address 0xE005 C000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
2
Table 137:I
I2C0CONCLR - address 0xE001 C018 and I2C1,
I2C1CONCLR - address 0xE005 C018) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
2
Table 138:I
address 0xE001 C004 and I2C1, I2C1STAT -
address 0xE005 C004) bit description . . . . . . 145
2
Table 139:I
0xE001 C008 and I2C1, I2C1DAT - address
0xE005 C008) bit description. . . . . . . . . . . . . 145
2
Table 140:I
I2C0, I2C0ADR - address 0xE001 C00C and
I2C1, I2C1ADR - address 0xE005 C00C)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 146
2
Table 141:I
I2C0SCLH - address 0xE001 C010 and I2C1,
I2C1SCLH - address 0xE005 C010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
2
Table 142:I
I2C0, I2C0SCLL - address 0xE001 C014 and
I2C1, I2C1SCLL - address 0xE005 C014)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 143:Example I
Table 144:Abbreviations used to describe an I
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 145:I2CONSET used to initialize Master Transmitter
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 146:I2C0ADR and I2C1ADR usage in Slave Receiver
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Table 147:I2C0CONSET and I2C1CONSET used to initialize
Slave Receiver mode . . . . . . . . . . . . . . . . . . . 149
Table 148:Master Transmitter mode . . . . . . . . . . . . . . . . 154
Table 149:Master Receiver mode . . . . . . . . . . . . . . . . . . 155
Table 150:Slave Receiver mode . . . . . . . . . . . . . . . . . . . 156
Rev. 01 — 15 August 2005
Chapter 25: Supplementary information
C Pin Description. . . . . . . . . . . . . . . . . . . . . 134
C register map . . . . . . . . . . . . . . . . . . . . . . . 142
C Control Set register (I2CONSET: I2C0,
C Control Set register (I2CONCLR: I2C0,
C Status register (I2STAT: I2C0, I2C0STAT -
C Data register (I2DAT: I2C0, I2C0DAT - address
C Slave Address register (I2ADR:
C SCL High Duty Cycle register (I2SCLH: I2C0,
C SCL Low Duty Cycle register (I2SCLL:
2
C clock rates. . . . . . . . . . . . . . . . . 147
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
UM10139
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C
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