Register Description - Philips LPC214 Series User Manual

Philips Semiconductors
Volume 1
the microcontroller. The same concern is present with the PLL1 and the USB. The
protection is accomplished by a feed sequence similar to that of the Watchdog Timer.
Details are provided in the description of the PLLFEED register.
Both PLLs are turned off and bypassed following a chip Reset and when by entering
Power-down mode. The PLL is enabled by software only. The program must configure and
activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source.

3.8.1 Register description

The PLL is controlled by the registers shown in
follow.
Warning: Improper setting of the PLL0 and PLL1 values may result in incorrect
operation of the device and the USB module!
Table 15: PLL registers
Generic Description
name
PLLCON PLL Control Register. Holding register for
updating PLL control bits. Values written to this
register do not take effect until a valid PLL feed
sequence has taken place.
PLLCFG PLL Configuration Register. Holding register for
updating PLL configuration values. Values
written to this register do not take effect until a
valid PLL feed sequence has taken place.
PLLSTAT PLL Status Register. Read-back register for PLL
control and configuration information. If
PLLCON or PLLCFG have been written to, but a
PLL feed sequence has not yet occurred, they
will not reflect the current PLL state. Reading
this register provides the actual values
controlling the PLL, as well as the status of the
PLL.
PLLFEED PLL Feed Register. This register enables
loading of the PLL control and configuration
information from the PLLCON and PLLCFG
registers into the shadow registers that actually
affect PLL operation.
[1]
User manual
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Rev. 01 — 15 August 2005
Chapter 3: System Control Block
Table 15. More detailed descriptions
Access Reset System clock
[1]
value (PLL0)
Address & Name
R/W 0 0xE01F C080
PLL0CON
R/W 0 0xE01F C084
PLL0CFG
RO 0 0xE01F C088
PLL0STAT
WO NA 0xE01F C08C
PLL0FEED
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
UM10139
USB 48 MHz
clock (PLL1)
Address & Name
0xE01F C0A0
PLL1CON
0xE01F C0A4
PLL1CFG
0xE01F C0A8
PLL1STAT
0xE01F C0AC
PLL1FEED
28