Usb Endpoint Interrupt Status Register (Usbepintst - 0Xe009 0030) - Philips LPC214 Series User Manual

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Volume 1
interrupts will be routed to the low priority interrupt line if the EP_FAST bit is set to 0,
irrespective of the Endpoint Interrupt Priority register
USBDevIntPri is a write only register.
Table 184: USB Device Interrupt Priority register (USBDevIntPri - address 0xE009 002C) bit description
Bit Symbol Value
0 FRAME 0
1
1 EP_FAST 0
1
7:2 - -

14.7.7 USB Endpoint Interrupt Status register (USBEpIntSt - 0xE009 0030)

Each physical non-isochronous endpoint is represented by one bit in this register to
indicate that it has generated the interrupt. All non-isochronous OUT endpoints give an
interrupt when they receive a packet without any error. All non-isochronous IN endpoints
will give an interrupt when a packet is successfully transmitted or a NAK handshake is
sent on the bus provided that the interrupt on NAK feature is enabled. Isochronous
endpoint transfer takes place with respect to frame interrupt. The USBEpIntSt is a read
only register.
Table 185: USB Endpoint Interrupt Status register (USBEpIntSt - address 0xE009 0030) bit allocation
Reset value: 0x0000 0000
Bit 31
Symbol EP15TX
Bit 23
Symbol EP11TX
Bit 15
Symbol EP7TX
Bit 7
Symbol EP3TX
Table 186: USB Endpoint Interrupt Status register (USBEpIntSt - address 0xE009 0030) bit description
Bit Symbol Description
0 EP0RX Endpoint 0, Data Received Interrupt bit.
1 EP0TX Endpoint 0, Data Transmitted Interrupt bit or sent a NAK.
2 EP1RX Endpoint 1, Data Received Interrupt bit.
3 EP1TX Endpoint 1, Data Transmitted Interrupt bit or sent a NAK.
4 EP2RX Endpoint 2, Data Received Interrupt bit.
5 EP2TX Endpoint 2, Data Transmitted Interrupt bit or sent a NAK.
6 EP3RX Endpoint 3, Isochronous endpoint.
7 EP3TX Endpoint 3, Isochronous endpoint.
8 EP4RX Endpoint 4, Data Received Interrupt bit.
9 EP4TX Endpoint 4, Data Transmitted Interrupt bit or sent a NAK.
10 EP5RX Endpoint 5, Data Received Interrupt bit.
9397 750 XXXXX
User manual
Description
FRAME interrupt is routed to the low priority interrupt line.
FRAME interrupt is routed to the high priority interrupt line.
EP_FAST interrupt is routed to the low priority interrupt line.
EP_FAST interrupt is routed to the high priority interrupt line.
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
30 29
EP15RX EP14TX
22 21
EP11RX EP10TX
14 13
EP7RX EP6TX
6 5
EP3RX EP2TX
Rev. 01 — 15 August 2005
Chapter 14: USB Device Controller
28 27
EP14RX EP13TX
20 19
EP10RX EP9TX
12 11
EP6RX EP5TX
4 3
EP2RX EP1TX
UM10139
(Section 14.7.11) setting. The
26 25
EP13RX EP12TX
18 17
EP9RX EP8TX
10 9
EP5RX EP4TX
2 1
EP1RX EP0TX
Reset value
0
0
0
0
0
0
NA
NA
0
0
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Reset value
0
0
NA
24
EP12RX
16
EP8RX
8
EP4RX
0
EP0RX
204